Silicon Investor - New Technology

[FJB] Microsoft’s New Quantum Computer, Summed Up In 3 Words Trevo...

FJB — 2/23/2025 3:38:58 PM

Microsoft’s New Quantum Computer, Summed Up In 3 Words
Trevor Filseth

nationalinterest.org

By creating a new state of matter, Microsoft’s engineers have ensured their quantum computer is truly one-of-a-kind. Everyone is fixated on the race for artificial intelligence dominance. Few, however, are taking the quest for quantum supremacy seriously. They should not lose sight of this—especially because Microsoft has just made what they claim to be a significant breakthrough in the mission to be the leader of the quantum computing revolution.

Microsoft’s “Majorana 1” Quantum Chip It’s called “Majorana 1,” and Microsoft says it is the world’s first Quantum Processing Unit (QPU) powered by what’s known as a topological core, which is designed to scale to a million qubits on a single chip. And the chip in question—what Microsoft calls a “topoconductor,” short for topological conductor—can fit into the palm of your hand.

The “Majorana 1” device gets its name from “Majorana Zero Modes” (MZMs). An MZM is a unique quantum particle that exists at the edges of certain materials (such as what the Majorana 1 is made of). They must exist in a state of absolute zero to operate. What’s more, they allow for rapid processing of highly complex problems at a very low error rate.

That’s the key aspect of quantum computing that people don’t seem to understand. It’s the speed of the processing. Quantum computers can solve highly complex problems very quickly. Specifically, it can solve the kinds of complex problems that traditional supercomputers either cannot solve or would take far too long to resolve.

Understanding the Physics Quantum computers work on an entirely different level of physics than do conventional computers.

Classical computers operate on binary bits. The quantum computer, however, works according to “quantum bits” (or “qubits”). Whereas binary bits can either be one or zero, a qubit can exist in multiple states. In other words, that zero and one can exist either separately, as one or zero, or—and here’s where things get weird for most people—the zero or one can exist simultaneously.

This is where you start to see people on The Joe Rogan Experience talking about quantum computing being the gateway for peering into multiple universes. That’s because, in order to quickly resolve a complex problem set a quantum computer is presented with, the quantum computer essentially looks at all possibilities and then seeks a resolution based on the best probable result.

And this is where things get dicey for the scientists working on quantum computers. Ordinarily, quantum computers have a high error rate.

The Microsoft team that has developed Majorana 1 says they’ve created a device that has reliable “quantum error correction” (QEC). Essentially, Microsoft claims that they’ve created a fault-tolerant quantum computer. Being fault tolerant is key.

Majorana-1 can continue functioning accurately even though occasional errors in qubits and gates will arise. One of the ways that Microsoft has ensured their new system has a relatively low QEC (around one percent error rate, which the engineers think they can reduce more over time), is via digital control that allows for computer engineers “to manage the large numbers of qubits needed for real-world applications.”

Low Error Rates Microsoft claims to have achieved topoconductor superconductivity—meaning they’ve created an entirely new class of material, which is what separates the Majorana-1 from other quantum computers today. This new material is what allows Microsoft to have a digitally controlled, small, and very fast qubit running its quantum computer.

By creating a new state of matter, Microsoft’s engineers have ensured their quantum computer is truly one-of-a-kind. That, in turn, likely means that Microsoft (at least for now) has quantum supremacy over its rivals.

Microsoft’s Quantum Chip: A Technological Breakthrough Quantum computing is suddenly all over the news. That’s likely because the tech sector is increasingly consumed with the objective of developing artificial intelligence. For AI to work well, it needs massive amounts of energy, data, and processing power. Quantum computers will give AI the processing power it needs to be truly dominant, if the engineers can make quantum computing viable and scalable. It appears that Microsoft has taken the first step towards doing that.

Of course, there are detractors. Some experts argue that it’s all hype—not just what Microsoft is saying but what many of these quantum computing firms are claiming to have achieved in their research and development.

DARPA’s Role The fact that the Microsoft program was “part of the final phase of the Defense Advanced Research Projects Agency (DARPA) Underexplored Systems for Utility-Scale Quantum Computer (US2QC) program,” as reported by Microsoft itself, means that this is not just a baseless claim meant to generate buzz for the tech company.

After all, DARPA is the group that has had its hand in some of the country’s most significant scientific and technological breakthroughs (most notably the Internet).

Lastly, the role of DARPA should not be overlooked because of the obvious national security implications (and complications) that quantum computing poses. Notably, modern encryption techniques can be easily hacked by quantum computers—as China’s quantum computer alarmingly demonstrated recently. Further, if paired to AI, an effective and scalable quantum computer could be lethal on the future battlefield.

Don’t forget, too, that, as cryptocurrencies are taking off, some security analysts fear that quantum computers could hack the blockchain technology that undergirds cryptocurrencies.

All these developments point to not only a revolution of AI, but a concomitant revolution in quantum computing—something that Microsoft itself has said they are spearheading.

So, even amid the other revolutionary advances in technology that have come to the fore this decade, keep your eye out for quantum computing. It’s coming sooner than most want to admit.

Brandon J. Weichert, a Senior National Security Editor at The National Interest as well as a Senior Fellow at the Center for the National Interest, and a contributor at Popular Mechanics, consults regularly with various government institutions and private organizations on geopolitical issues. Weichert’s writings have appeared in multiple publications, including the Washington Times, National Review, The American Spectator, MSN, the Asia Times, and countless others. His books include Winning Space: How America Remains a Superpower, Biohacked: China’s Race to Control Life, and The Shadow War: Iran’s Quest for Supremacy. His newest book, A Disaster of Our Own Making: How the West Lost Ukraine is available for purchase wherever books are sold. He can be followed via Twitter @WeTheBrandon.

Image: Shutterstock.

[FJB] [X] Nice work by @xAI team, @X team, @Nvidia & supporting companies getting Mem...

FJB — 7/22/2024 2:41:11 PM

[X]

Nice work by @xAI team, @X team, @Nvidia & supporting companies getting Memphis Supercluster training started at ~4:20am local time.

With 100k liquid-cooled H100s on a single RDMA fabric, it’s the most powerful AI training cluster in the world!
— Elon Musk (@elonmusk) July 22, 2024

[/X]

[FJB] Intel Vs. Samsung Vs. TSMC semiengineering.com Ed Sperling 21–26 minutes ...

FJB — 7/21/2024 10:43:05 AM

Intel Vs. Samsung Vs. TSMC

semiengineering.com

Ed Sperling

21–26 minutes

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs.

Unlike in the past, when a single industry roadmap dictated how to get to the next process node, the three largest foundries increasingly are forging their own paths. They all are heading in the same general direction with 3D transistors and packages, a slew of enabling and expansive technologies, and much larger and more diverse ecosystems. But some key differences are emerging in their methodologies, architectures, and third-party enablement.

Roadmaps for all three show that transistor scaling will continue at least into the 18/16/14 angstrom range, with a possible move from nanosheets and forksheet FETs, followed by complementary FETs (CFETs) at some point in the future. The key drivers are AI/ML and the explosion of data that needs to be processed, and in most cases these will involve arrays of processing elements, usually with high levels of redundancy and homogeneity, in order to achieve higher yields.

In other cases, these designs may contain dozens or hundreds of chiplets, some engineered for specific data types and others for more general processing. Those chiplets can be mounted on a substrate in a 2.5D configuration, an approach that has gained traction in data centers because it simplifies the integration of high-bandwidth memory ( HBM), as well as in mobile devices, which also include other features such as image sensors, power supplies, and additional digital logic used for non-critical functions. All three foundries are working on full 3D-ICs, as well. And there will be hybrid options available, where logic is stacked on logic and mounted on a substrate, but separated from other features in order to minimize physical effects such as heat — a heterogeneous configuration that has been called both 3.5D and 5.5D.

Rapid and mass customization
One of the biggest changes involves bringing domain-specific designs to market much more quickly than in the past. Mundane as this may sound, it’s a competitive necessity for many leading-edge chips, and it requires fundamental changes in the way chips are designed, manufactured, and packaged. Making this scheme work demands a combination of standards, innovative connectivity schemes, and a mix of engineering disciplines that in the past had limited interactions, if any.

Sometimes referred to as “mass customization,” it includes the usual power, performance, and area/cost (PPA/C) tradeoffs, as well as rapid assembly options. That is the promise of heterogeneous chiplet assemblies, and from a scaling perspective it marks the next phase of Moore’s Law. The entire semiconductor ecosystem has been laying the groundwork for this shift incrementally for more than a decade.

But getting heterogeneous chiplets — essentially hardened IP from multiple vendors and foundries — to work together is both a necessary and daunting engineering challenge. The first step is connecting the chiplets together in a consistent way to achieve predictable results, and this is where the foundries have spent much of their effort, particularly with the Universal Chiplet Interconnect Express (UCIe) and Bunch of Wires (BoW) standards. While that connectivity is a critical requirement for all three, it’s also one of the main areas of divergence.

Intel Foundry’s current solution, prior to fully integrated 3D-ICs, is to develop what industry sources describe as “sockets” for chiplets. Instead of characterizing each chiplet for a commercial marketplace, the company defines the specification and the interface so that chiplet vendors can develop these limited-function mini-chips to meet those specs. That addresses one of the big stumbling blocks for a commercial chiplet marketplace. All the pieces need to work together, from data speed to thermal and noise management.

Intel’s scheme relies heavily on its Embedded Multi-Die Interconnect Bridge (EMIB), first introduced in 2014. “The really cool thing about an EMIB base is you can add any amount of chiplets,” said Lalitha Immaneni, vice president of technology development at Intel. “We don’t have a limitation on the number of IPs that we can use in design, and it won’t increase the interposer size, so it’s cost-effective and it’s agnostic of the process. We have given out a package assembly design kit, which is like your traditional PDK for the assembly. We give them the design rules, the reference flows, and we tell them the allowable constructions. It will also give them any collaterals that we need to take it into our assembly.”

Depending upon the design, there can be multiple EMIBs in a package, complemented by thermal interface materials (TIMs), in order to dissipate heat that can become trapped inside a package. TIMs typically are pads that are engineered to conduct heat away from the source, and they are becoming more common as the amount of compute inside a package increases and as the substrates are thinned to shorten the distance signals need to travel.

But the thinner the substrate, the less effective it is at heat dissipation, which can result in thermal gradients that are workload-dependent and therefore difficult to anticipate. Eliminating that heat may require TIMs, additional heat sinks, and potentially even more exotic cooling approaches such as microfluidics.

Both TSMC and Samsung offer bridges, as well. Samsung has embedded bridges inside the RDL — an approach it calls 2.3D or I-Cube ETM — and it’s using them to connect sub-systems to those bridges in order to speed time to working silicon. Instead of relying on a socket approach, some of the integration work will be pre-done in known-good modules.

“Putting together two, four, or eight CPUs into a system is something that very sophisticated customers know how to go out and do,” said Arm CEO Rene Haas, in a keynote speech at a recent Samsung Foundry event. “But if you want to build an SoC that has 128 CPUs attached to a neural network, memory structures, interrupt controllers that interface to an NPU, an off-chip bus to go to another chiplet, that is a lot of work. In the last year and a half, we’ve seen a rush of people building these complex SoCs wanting more from us.”

Samsung also has been building mini-consortia [1] of chiplet providers, targeted at specific markets. The initial concept is that one company builds an I/O die, another builds the interconnect, and a third builds the logic, and when that is proven to work, then others are added into the mix to provide more choices for customers.

TSMC has experimented with a number of different options, including both RDL and non-RDL bridges, fan-outs, 2.5D chip-on-wafer-on-substrate (CoWoS), and System On Integrated Chips (SoIC), a 3D-IC concept in which chiplets are packed and stacked inside a substrate using very short interconnects. In fact, TSMC has a process design kit for just about every application, and it has been active in creating assembly design kits for advanced packaging, including reference designs to go with them.

The challenge is that foundry customers willing to invest in these complex packages increasingly want very customized solutions. To facilitate that, TSMC rolled out a new language called 3Dblox, a top-down design scheme that fuses physical and connectivity constructs, allowing assertions to be applied across both. This sandbox approach allows customers to leverage any of its packaging approaches — InFO, CoWoS, and SoIC. It’s also essential to TSMC’s business model, because the company is the only pure-play foundry of the three [2] — although both Intel and Samsung have distanced their foundry operations in recent months.

“We started from a concept of modularization,” said Jim Chang, vice president of advanced technology and mask engineering at TSMC, in a presentation when 3Dblox was first introduced in 2023. “We can build a full 3D-IC stacking with this kind of language syntax plus assertions.”

Chang said the genesis of this was a lack of consistency between the physical and connectivity design tools. But he added that once this approach was developed, it also enabled reuse of chiplets in different designs because much of the characterization was already well-defined and the designs are modular.

Fig. 1: TSMC’s 3Dblox approach. Source: TSMC

Samsung followed with its own system description language, 3DCODE, in December 2023. Both Samsung and TSMC claim their languages are standards, but they’re more like new foundry rule decks because it’s unlikely these languages will be used outside of their own ecosystems. Intel’s 2.5D approach doesn’t require a new language because the rules are dictated by the socket specification, trading off some customization with a shortened time to market and a simpler approach for chiplet developers.

The chiplet challenge
Chiplets have obvious benefits. They can be designed independently at whatever process node makes sense, which is particularly important for analog features. But figuring out how to put the pieces together with predictable results has been a major challenge. The initial LEGO-like architecture scheme floated by DARPA has proven much more complicated than first envisioned, and it has required a massive and ongoing efforts by broad ecosystems to make it work.

Chiplets need to be precisely synchronized so that critical data is processed, stored, and retrieved without delay. Otherwise, there can be timing issues, in which one computation is either delayed or out-of-sync with other computations, leading to delays and potential deadlocks. In the context of mission- or safety-critical applications, the loss of a fraction of a second can have serious consequences.

Simplifying the design process, particularly with domain-specific designs where one size does not fit all, is an incredibly complex endeavor. The goal for all three foundries is to provide more options for companies that will be developing high-performance, low-power chips. With an estimated 30% to 35% of all leading-edge design starts now in the hands of large systems companies such as Google, Meta, Microsoft, and Tesla, the economics of leading-edge chip and package design have changed significantly, and so have the PPA/C formulas and tradeoffs.

Chips developed for these systems companies probably will not be sold commercially. So if they can achieve higher performance per watt, then the design and manufacturing costs can be offset by lower cooling power and higher utilization rates — and potentially fewer servers. The reverse is true for chips sold into mobile devices and commodity servers, where high development costs can be amortized across huge volumes. The economics for customized designs in advanced packages work for both, but for very different reasons.

Scaling down, up, and out
It’s assumed that within these complex systems of chiplets there will be multiple types of processors, some highly specialized and others more general-purpose. At least some of these will likely be developed at the most advanced process nodes due to limited power budgets. Advanced nodes still provide higher energy efficiency, which allows more transistors to be packed into the same area in order to improve performance. This is critical for AI/ML applications, where processing more data faster requires more multiply/accumulate operations in highly parallel configurations. Smaller transistors provide greater energy efficiency, allowing more processing per square millimeter of silicon, but the gate structure needs to be changed to prevent leakage, which is why forksheet FETs and CFETs are on the horizon.

Put simply, process leadership still has value. Being first to market with a leading-edge process is good for business, but it’s only one piece of a much larger puzzle. All three foundries have announced plans to push well into the angstrom range. Intel plans to introduce its 18A this year, followed by 14A a couple years later.

Fig. 2: Intel’s process roadmap. Source: Intel Foundry

TSMC, meanwhile, will add A16 in 2027 (see figure 3, below.)

Fig. 3: TSMC’s scaling roadmap into the angstrom era. Source: TSMC

And Samsung will push to 14 angstroms sometime in 2027 with its SF1.4, apparently skipping 18/16 angstroms. (See figure 4)

Fig. 4: Samsung’s process scaling roadmap. Source: Samsung Foundry

From a process node standpoint, all three foundries are on the same track. But advances are no longer tied to the process node alone. The focus increasingly is about latency and performance per watt in a specific domain, and this is where stacking logic-on-logic in a true 3D-IC configuration will excel, using hybrid bonds to connect chiplets to a substrate and each other. Moving electrons through a wire on a planar die is still the fastest (assuming a signal doesn’t have to travel from one end of the die to another), but stacking transistors on top of other transistors is the next best thing, and in some cases even better than a planar SoC because some vertical signal paths may be shorter.

In a recent presentation, Taejoong Song, Samsung Foundry’s vice president of foundry business development, showed a roadmap featuring logic-on-logic mounted on a substrate, combining a 2nm (SF2) die on top of a 4nm (SF4X) die, both mounted on top of another substrate. This is basically a 3D-IC on a 2.5D package, which is the 3.5D or 5.5D concept mentioned earlier. Song said the foundry will begin stacking an SF1.4 on top of SF2P, starting in 2027. What’s particularly attractive about this approach are the thermal dissipation possibilities. With the logic separated from other functions, heat can be channeled away from the stacked dies through the substrate or any of the five exposed sides.

Fig. 5: Samsung’s 3D-IC architecture for AI. Source: Samsung

Intel, meanwhile, will leverage its Foveros Direct 3D to stack logic on logic, either face-to-face or face-to-back. The approach allows chips or wafers from different foundries, with the connection bandwidth determined by the copper via pitch, according to a new Intel white paper. The paper noted that the first version would use a copper pitch of 9µm, while the second generation would use a 3µm pitch.

Fig. 6: Intel’s Foveros Direct 3D. Source: Intel

“The true 3D-IC comes with Foveros, and then also with hybrid bonds,” said Intel’s Immaneni. “You cannot go in the tradition route of design where you put it together and run validation, and then find, ‘Oops, I have an issue.’ You cannot afford to do this anymore because you’re impacting your time to market. So you really want to provide a sandbox to make it predictable. But even before I step into this detailed design environment, I want to run my mechanical/electrical/thermal analysis. I want to look at the connectivity so I don’t have opens and shorts. The burden for 3D-IC resides more in the code design than the execution.”

Foveros allows an active logic die to be stacked on either another active or passive die, with the base die used to connect all the die in a package at a 36 micron pitch. By leveraging advanced sort, Intel claims it can guarantee 99% known good die, and 97% yield at post-assembly test.

TSMC’s CoWoS, meanwhile, already is in use by NVIDIA and AMD for their advanced packaging for AI chips. CoWoS is essentially a 2.5D approach, using an interposer to connect SoCs and HBM memory using through-silicon vias. The company’s plans for SoIC are more ambitious, packaging both memory on logic along with other elements, such as sensors, in a 3D-IC at the front end of the line. This can significantly reduce assembly time of multiple layers, sizes, and functions. TSMC contends that its bonding scheme enables faster and shorter connections than other 3D-IC approaches. One report said Apple will begin using TSMC’s SoIC technology starting next year, while AMD will expand its use of this approach.

Other innovations
Putting the process and packaging technology in place opens the door to a much broader set of competitive options. Unlike in the past, when big chipmakers, equipment vendors, and EDA companies defined the roadmap for chips, the chiplet world provides the tools for end customers to make those decisions. This is due, in no small part, to the number of features that can be put into a package versus those that can fit inside the reticle limits of an SoC. Packages can be expanded horizontally or vertically, as needed, and in some cases they can improve performance just through vertical floor-planning.

But given the vast opportunity in the cloud and the edge — particularly with the rollout of AI everywhere — the three big foundries, as well as their ecosystems, are racing to developing new capabilities and features. In some cases, this involves leveraging what they already have. In other cases, it requires brand new technologies.

For example, Samsung has started detailing plans about custom HBM, which includes 3D DRAM stacks with a configurable logic layer underneath. This is the second time around for this approach. Back in 2011, Samsung and Micron co-developed the Hybrid Memory Cube, packaging a DRAM stack on a layer of logic. HBM won the war after JEDEC turned it into a standard, and HMC largely disappeared. But there was nothing wrong with the HMC approach, other than perhaps bad timing.

In its new form, Samsung plans to offer customized HBM as an option. Memory is one of the key elements that determine performance, and the ability to read/write and move data back and forth more quickly between memory and processors can have a big impact on performance and power. And those numbers can be significantly better if the memory is right-sized to a specific workload or data type, and if some of the processing can be done inside the memory module so there is less data to move.

Fig. 7: Samsung roadmap and innovations. Source: Semiconductor Engineering/MemCon 2024

Intel, meanwhile, has been working on a better way to deliver power to densely packed transistors, a persistent problem as the transistor density and number of metal layers increases. In the past, power was delivered from the top of the chip down, but two problems have emerged at the most advanced nodes. One is the challenge of actually delivering enough power to every transistor. The second is noise, which can come from power, substrates, or electromagnetic interference. Without proper shielding — something that is becoming more difficult at each new node due to thinner dielectrics and wires — that noise can impact signal integrity.

Delivering power through the backside of a chip minimizes those kinds of issues and reduces wiring congestion. But it also adds other challenges, such as how to drill holes through a thinner substrate without structural damage. Intel apparently has solved these issues, with plans to offer its PowerVia backside power scheme this year.

TSMC said it plans to deliver backside power delivery at A16 in 2026/2027. Samsung is roughly on the same schedule, delivering it in the SF2Z 2nm process.

Intel also has announced plans for glass substrates, which can provide better planarity and lower defectivity than CMOS. This is especially important at advanced nodes, where even nano-sized pits can cause issues. As with backside power delivery, handling issues abound. The upside is that glass has the same coefficient of thermal expansion as silicon, so it is compatible with the expansion and contraction of silicon components, such as chiplets. After years of sitting on the sidelines, glass is suddenly very attractive. In fact, both TSMC and Samsung are working on glass substrates, as well, and the whole industry is starting to design with glass, handle it without cracking it, and to inspect it.

TSMC, meanwhile, has focused heavily on building an ecosystem and expanding its process offerings. Numerous industry sources say TSMC’s real strength is the ability to deliver process development kits for just about any process or package. The foundry produces about 90% of the most advanced chips globally, according to Nikkei. It also has the most experience with advanced packaging of any foundry, and the largest and broadest ecosystem, which is important.

That ecosystem is critical. The chip industry is so complex and varied that no single company can do everything. The question going forward will be how complete those ecosystems truly are, particularly if the number of processes continues to grow. For example, EDA vendors are essential enablers, and for any process or packaging approach to be successful, design teams need automation. But the more processes and packaging options, the more difficult it will be for EDA vendors to support every incremental change or improvement, and potentially the greater the lag time between announcement and delivery.

Conclusion
The recent supply chain glitches and geopolitics have convinced the United States and Europe that they need to re-shore and “friend-shore” manufacturing. The investments in semiconductor fabs, equipment, tools, and research are unprecedented. How that affects the three largest foundries remains to be seen, but it certainly is providing some of the impetus behind new technologies such as co-packaged optics, a raft of new materials, and cryogenic computing.

The impact of all of these changes on market share is becoming harder to track. It’s no longer about which foundry is producing chips at the smallest process node, or even the number of chips being shipped. A single advanced package may have dozens of chiplets. The real key is the ability to deliver solutions that matter to customers, quickly and efficiently. In some cases the driver will be performance per watt, while in others it may be time to results with power as a secondary consideration. And in still others, it may be a combination of features that only one of the leading-edge foundries can provide in sufficient quantity. But what is clear is that the foundry race is significantly more complex than ever before, and becoming more so. In this highly complex world, simple metrics for comparison no longer apply.

References
1. Mini-Consortia Forming Around Chiplets, March 20, 2023; E. Sperling/Semiconductor Engineering
2. TSMC also is the largest shareholder (35%) in Global Unichip Corp., a design services company.

[FJB] compression utility written in Haskell lazamar.github.io

FJB — 7/4/2024 3:14:28 AM

[lianass] I

lianass — 5/17/2024 11:14:23 AM

[FJB] HOW TO USE AI oneusefulthing.org How to Use AI to Do Stuff: An Opin...

FJB — 7/16/2023 10:53:47 AM

HOW TO USE AI

oneusefulthing.org

How to Use AI to Do Stuff: An Opinionated Guide
Ethan Mollick

15–19 minutes

Discover more from One Useful Thing
Translating academic research into mostly useful insights, with some ephemera on the side. Mostly AI stuff recently. By Prof. Ethan Mollick

How to Use AI to Do Stuff: An Opinionated GuideCovering the state of play as of Summer, 2023

Increasingly powerful AI systems are being released at an increasingly rapid pace. This week saw the debut of Claude 2, likely the second most capable AI system available to the public. The week before, Open AI released Code Interpreter, the most sophisticated mode of AI yet available. The week before that, some AIs got the ability to see images.

And yet not a single AI lab seems to have provided any user documentation. Instead, the only user guides out there appear to be Twitter influencer threads. Documentation-by-rumor is a weird choice for organizations claiming to be concerned about proper use of their technologies, but here we are.

I can’t claim that this is going to be a complete user guide, but it will serve as a bit of orientation to the current state of AI. I have been putting together a Getting Started Guide to AI for my students (and interested readers) every few months, and each time, it requires major modifications. The last couple of months have been particularly insane.

This guide is opinionated, based on my experience, and focused on how to pick the right tool to do things. I have written separately about the kinds of tasks you may want AI to do, which might be useful to read first.

When we talk about AI right now, we are usually talking about Large Language Models, or LLMs. Most AI applications are powered by LLMs, of which there are just a few Foundation Models, created by a handful of organizations. Each company gives direct access to their models via a Chatbot: OpenAI makes GPT-3.5 and GPT-4, which power ChatGPT and Microsoft’s Bing (access it on an Edge browser). Google has a variety of models under the label of Bard. And Anthropic makes Claude and Claude 2.

There are other LLMs I won’t be discussing. The first is Pi, a chatbot built by Inflection. Pi is optimized for conversation, and really, really wants to be your friend (seriously, try it to see what I mean). It does not like to do much besides chat, and trying to get it to do work for you is an exercise in frustration. We also won’t cover the variety of open source models that anyone can use and modify. They are generally not accessible or useful for the casual user today, but have real promise. Future guides may include them.

So here is your quick reference chart, summarizing the state of LLMs:

The first four (including Bing) are all OpenAI systems. There are basically two major OpenAI AIs today: 3.5 and 4. The 3.5 model kicked off the current AI craze in November, the 4 model premiered in the Spring and is much more powerful. A new variation uses plugins to connect to the internet and other apps. There are a lot of plugins, most of which are not very useful, but you should feel free to explore them as needed. Code Interpreter as is an extremely powerful version of ChatGPT that can run Python programs. If you have never paid for OpenAI, you have only used 3.5. Aside from the plugins variation, and a temporarily suspended version of GPT-4 with browsing, none of these models are connected to the internet. Microsoft’s Bing uses a mix of 4 and 3.5, and is usually the first model in the GPT-4 family to roll out new features. For example, it can both create and view images, and it can read documents in the web browser. It is connected to the internet. Bing is a bit weird to use, but powerful.

Google has been testing its own AI for consumer use, which they call Bard, but which is powered by a variety of Foundation Models, most recently one called PaLM 2. For the company that developed LLM technology, they have been pretty disappointing, although improvements announced yesterday show they are still working on the underlying technology, so I have hope. It has already gained the capability to run limited code and interpret images, but I would generally avoid it for now.

The final company, Anthropic has released Claude 2. Claude is most notable for having a very large context window - essentially the memory of the LLM. Claude can hold almost an entire book, or many PDFs, in memory. It has been built to be less likely to act maliciously than other Large Language Models, which means, practically, that it tends to scold you a bit about stuff.

Now, on to some uses:

Best free options: Bing and Claude 2
Paid option: ChatGPT 4.0/ChatGPT with plugins

For right now, GPT-4 is still the most capable AI tool for writing, which you can access at Bing (select“creative mode”) for free or by purchasing a $20/month subscription to ChatGPT. Claude, however, is a close second, and has a limited free option available.

These tools are also being integrated directly into common office applications. Microsoft Office will include a copilot powered by GPT and Google Docs will integrate suggestions from Bard. The implications of what these new innovations mean for writing are pretty profound.

Here are some ways to use AI to help you write.

Writing drafts of anything. Blog posts, essays, promotional material, speeches, lectures, chose-you-own adventures, scripts, short stories - you name it, AI does it, and pretty well. All you have to do is prompt it. Prompt crafting is not magic, but basic prompts result in boring writing, but getting better at prompting is not that hard, just work interactively with the system. You will find AI systems to be much more capable as writers with a little practice.
Make your writing better. Paste your text into an AI. Ask it to improve the content, or for suggestions about how to make it better for a particular audience. Ask it to create 10 drafts in radically different styles. Ask it to make things more vivid, or add examples. Use it to inspire you to do better work.
Help you with tasks. AI can do things you don’t have the time to do. Use it like an intern to write emails, create sales templates, give you next steps in a business plan, and a lot more. Here is what I could accomplish with it in 30 minutes in supporting a product launch.
Unblock yourself. It is very easy to get distracted from a task by one difficult challenge. AI provides a way of giving yourself momentum.

Some things to worry about: In a bid to respond to your answers, it is very easy for the AI to “hallucinate” and generate plausible facts. It can generate entirely false content that is utterly convincing. Let me emphasize that: AI lies continuously and well. Every fact or piece of information it tells you may be incorrect. You will need to check it all. Particularly dangerous is asking it for references, quotes, citations, and information for the internet (for the models that are not connected to the internet). Bing will usually hallucinate less than other models, because GPT-4 is generally more grounded and because Bing’s internet connection means it can actually pull in relevant facts. Here is a guide to avoiding hallucinations, but they are impossible to completely eliminate.

And also note that AI doesn’t explain itself, it only makes you think it does. If you ask it to explain why it wrote something, it will give you a plausible answer that is completely made up. When you ask it for its thought process, is not interrogating its own actions, it is just generating text that sounds like it is doing so. This makes understanding biases in the system very challenging, even though those biases almost certainly exist.

It also can be used unethically to manipulate or cheat. You are responsible for the output of these tools.

Stable Diffusion, which is open source and you can run from any high-end computer. It takes effort to get started, since you have to learn to craft prompts properly, but once you do it can produce great results. It is especially good for combining AI with images from other sources. Here is a nice guide to Stable Diffusion if you go that route (be sure to read both parts 1 and part 2).
DALL-E, from OpenAI, which is incorporated into Bing (you have to use creative mode) and Bing image creator. This system is solid, but worse than Midjourney.
Midjourney, which is the best system in mid-2023. It has the lowest learning-curve of any system: just type in "thing-you-want-to-see --v 5.2" (the --v 5.2 at the end is important, it uses the latest model) and you get a great result. Midjourney requires Discord. Here is a guide to using Discord.
Adobe Firefly, built into a variety of Adobe products, but it lags DALL-E and Midjourney in terms of quality. However, while the other two models have been unclear about the source images that they used to train their AIs, Adobe has declared that it is only using images it has the right to use.

Here is how they compare (each image is labelled with the model):

Prompt: “Fashion photoshoot of sneakers inspired by Van Gogh” - the first images that were created by each model
Some things to worry about: These systems are built around models that have built-in biases due to their training on Internet data (if you ask it to create a picture of an entrepreneur, for example, you will likely see more pictures featuring men than women, unless you specify “female entrepreneur”), you can use this explorer to see these biases at work.

These systems are also trained on existing art on the internet in ways that are not transparent and potentially legally and ethically questionable. Though technically you own copyright of the images created, legal rules are still hazy.

Also, right now, they don’t create text, just a bunch of stuff that looks like text. But Midjourney has nailed hands.

Best free option: Bing
Paid option: ChatGPT 4.0, but Bing is likely better because of its internet connections

Despite of (or in fact, because of) all its constraints and weirdness, AI is perfect for idea generation. You often need to have a lot of ideas to have good ideas, and AI is good at volume. With the right prompting, you can also force it to be very creative. Ask Bing in creative mode to look up your favorite unusual idea generation techniques, like Brian Eno's oblique strategies or Mashall McLuhan's tetrads, and apply them. Or ask for something weird, like ideas inspired by a random patent, or your favorite superhero…

Best animation tool: D-iD for animating faces in videos. Runway v2 for creating videos from text
Best voice cloning: ElevenLabs

It is now trivial to generate a video with a completely AI generated character, reading a completely AI-written script, talking in an AI-made voice, animated by AI. It can also deepfake people, as you can see in this link where I deepfaked myself. Instructions and more information here. Use with caution, but this can be great for explainer videos and introductions.

The first commercially available text-to-video tool was also recently released, Runway v2. It creates short 4-second clips, and is more of a demonstration of what is to come, but is worth taking a look at if you want a sense of the future development in this space.

Some things to worry about: Deep fakes are a huge concern, and these systems need to be used ethically.

For data (And also any weird ideas you have with code): Code Interpreter
For documents: Claude 2 for large documents or many documents at once, Bing Sidebar for smaller documents and webpages (the sidebar, part of the Edge browsers can “see” what is in your browser, letting Bing work with that information, though the size of the context window is limited)

I wrote about Code Interpreter last week. It is a mode of GPT-4 that lets you upload files to the AI, allows the AI to write and run code, and lets you download the results provided by the AI. It can be used to execute programs, run data analysis (though you will need to know enough about statistics and data to check its work), and create all sorts of files, web pages, and even games. Though there has been a lot of debate since its release about the risks associated with untrained people using it for analysis, many experts testing Code Interpreter are pretty impressed, to the degree that one paper suggests it will require changing the way we train data scientists. Go to my previous post if you want more details on how to use it. I also made an initial prompt to set up Code Interpreter to create useful data visualizations. It gives it some basic principles of good chart design & also reminds it that it can output many kinds of files. You can find that here.

For working with text, and especially PDFs, Claude 2 is excellent so far. I have pasted in entire books into the previous version of Claude, with impressive results, and the new model is much stronger. You can see my previous experience, and some prompts that might be interesting to use, here. I also gave it numerous complex academic articles and asked it to summarize the results, and it does a good job! Even better, you can then interrogate the material by asking follow-up questions: what is the evidence for that approach? What do the authors conclude? And so on…

Some things to worry about: These systems still hallucinate, though in more limited ways. You need to check over their results if you want to ensure accuracy.

Best free option: Bing
Paid option: Usually Bing is best. For children, Khanmigo from Khan Academy offers good AI-driven tutoring powered by GPT-4.

If you are going to use AI as a search engine, probably don’t do that. The risk of hallucination is high and most AIs are not connected to the Internet, anyway (which is why I suggest you use Bing. Bard, Google’s AI, hallucinates much more). However, there is some evidence that AI can often provide more useful answers than search when used carefully, according to a recent pilot study. Especially in cases where search engines aren’t very good, like tech support, deciding where to eat, or getting advice, Bing is often better than Google as a starting point. This is an area that is evolving rapidly, but you should be careful about these uses for now. You don’t want to get in trouble.

But more exciting is the possibility of using AIs to help education, including helping us learn. I have written about how AI can be used for teaching and to help make teachers’ lives easier and their lessons more effective, but it can also work for self-guided learning as well. You can ask the AI to explain concepts and get ver good results. This prompt is a good automated tutor, and use can find a direct link to activate the tutor in ChatGPT here. Because we know the AI could be hallucinating, you would be wise to (carefully!) double-check any critical data against another source.

Thanks to rapid advances in technology, these are likely the worst AI tools you will ever use, as the past few months of development have shown. I have no doubt I will need to make a new guide soon. But remember two key points that remain true about AI:

AI is a tool. It is not always the right tool. Consider carefully whether, given its weaknesses, it is right for the purpose to which you are planning to apply it.
There are many ethical concerns you need to be aware of. AI can be used to infringe on copyright, or to cheat, or to steal the work of others, or to manipulate. And how a particular AI model is built and who benefits from its use are often complex issues, and not particularly clear at this stage. Ultimately, you are responsible for using these tools in an ethical manner.

We are in the early days of a very rapidly advancing revolution. Are there other uses you want to share? Let me know in the comments.

This post is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

[FJB] Reverse Engineering Tiktok's VM Obfuscation (Part 1) Thu Dec 22 2022 authored b...

FJB — 12/24/2022 5:07:20 PM

Reverse Engineering Tiktok's VM Obfuscation (Part 1)
Thu Dec 22 2022

authored by veritas
TikTok has a reputation for its aggressive data collection. In fact, an article published on 22 December 2022 uncovered how ByteDance spied on multiple Forbes journalists using TikTok. While some of the data they collect may seem benign, it can be used to build a detailed profile of each user. Information such as user location, device type, and various hardware metrics are combined to create a unique "fingerprint" that can potentially be used to track a user's activity on and off the app. This data may also be used to prevent their APIs from being utilized in automated scripts by ensuring that the data from the requests seem humanlike.

The platform has implemented various methods to make it difficult for reverse-engineers to understand exactly what data is being collected and how it is being used. Analyzing the call stack of a request made on tiktok.com can begin to paint the picture for us. Let's start by doing a search for the term "food". Upon pressing enter, TikTok sends off a GET request with our search term and some extra telemetry embedded.

CONT...

nullpt.rs

[FJB] [youtube video]

FJB — 11/6/2022 10:51:09 AM

[FJB] NEXT WAVE IS MOVING AWAY FROM CLOUD. IT IS KIND OF A RIP OFF... levelup.gitcon...

FJB — 9/28/2022 6:02:18 PM

NEXT WAVE IS MOVING AWAY FROM CLOUD. IT IS KIND OF A RIP OFF...

levelup.gitconnected.com

How we reduced our annual server costs by 80% — from $1M to $200k — by moving away from AWS
Trey Huffine

An interview with Zsolt Varga, the tech lead and general manager at Prerender

This week we interviewed Zsot Varga, the lead engineer and manager at Prerender.io. He shares how Prerender saved $800k by removing their reliance on AWS and building in-house infrastructure to handle traffic and cached data.

“The goal was to reduce costs while maintaining the same speed of rendering and quality of service. Migrations like this need to be carefully planned and executed, as incorrect configuration or poor execution, would cause downtime for customer web pages and social media clicks and make their search rankings suffer and potentially increase our churn rate.”

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Can you describe Prerender and the most interesting technical problem you’re solvingPrerender, in simple terms, caches and prerenders your JavaScript pages so search engines can have a pure HTML file to crawl and index, and all it needs is to have the proper middleware installed on the site, avoiding users the pain of costly and long JavaScript workarounds.

However, all this data and processes need to happen on a server and, of course, we used AWS for it. A few years of growth later, we’re handling over 70,000 pages per minute, storing around 560 million pages, and paying well over $1,000,000 per year.

Or at least we would be paying that much if we stayed with AWS. Instead, we were able to cut costs by 80% in a little over three months with some out-of-the-box thinking and a clear plan. Here’s how you could too.

Planning a Migration: Our Step-by-Step GuideUp until recently, Prerender stored the pages it caches and renders for its clients using servers and services hosted on Amazon Web Services (AWS) — being AWS one of the largest cloud providers, offering virtual servers and managed services.

Prerender had hitherto used AWS to store the pages it cached until they were ready to be picked up by Google, Facebook, or any other bot/spider looking for content to be indexed. This provided much of Prerender’s functionality — delivering static HTML to Google and other search engines, and dynamic, interactive JavaScript to human users.

The problem? Storing multiple terabytes of prerendered web page contents in this way on a 3rd party server is hugely expensive. Storing the cached pages in this way was costing Prerender astronomical amounts of money in maintenance and hosting fees alone.

But there was another catch that not many start-ups take into account and there’s not too much of a conversation around it: traffic cost.

Getting data into AWS is technically free, but what good is static data for most software? When moving the data around it became a huge cost for Prerender and we started to notice the bottleneck that was holding us back.

The solution? Migrate the cached pages and traffic onto Prerender’s own internal servers and cut our reliance on AWS as quickly as possible.

When we did a cost projection we estimated that we could reduce our hosting fees by 40%, and decided a server migration would save both Prerender and our client’s money.

The goal was to reduce costs while maintaining the same speed of rendering and quality of service. Migrations like this need to be carefully planned and executed, as incorrect configuration or poor execution, would cause downtime for customer web pages and social media clicks and make their search rankings suffer and potentially increase our churn rate.

To mitigate the potential consequences, we planned a three-phase process by which we could easily revert back to the previous step if anything went wrong. If for whatever reason the new servers didn’t work, we could easily roll back our changes without any downtime or service degradation noticeable to customers.

The caveat with continual and systematic testing is that it takes place over weeks and months.

Moving Prerender Away From AWS: a Weekly OverviewPhase 1 — Testing (4 to 6 Weeks)Phase 1 mostly involved setting up the bare metal servers and testing the migration on a small and more manageable setting before scaling. This phase required minimal software adaptation, which we decided to run on KVM virtualization on Linux.

In early May, the first batch of servers was running, and 1% of Prerender traffic was directed to the new servers. Two weeks into the migration, we were already saving $800 a day. By the end of the month, we’d migrated most of the traffic workloads away from AWS, reducing the daily chrome rendering workloads costs by 45%.

On the server-side, our cost was currently at $13K per month. Combined with AWS, we had already cut our expenses by 22%.

The testing phase was crucial to make sure the following processes would run smoothly. We worked on improving the system robustness with more monitoring & better error handling. Besides the server monitoring dashboard we already had, we also set up a new rendering monitoring dashboard to be able to spot any error or performance issue that occurred.

Thanks to our constant monitoring and clear communication, tests were successful, our savings projections were exceeded and everything was in place to start phase 2 of the migration.

Phase 2 — Technical Set-Up (4 Weeks)The migration period between June and early July was mostly technical set-up after the first phase of the migration served as a proof of concept. Implementation of the second phase mostly involved moving the cache storage to the bare metal servers.

When the migration reached mid-June, we had 300 servers running very smoothly with a total 200 million cached pages. We used Apache Cassandra nodes on each of the servers that were compatible with AWS S3.

We broke the online migration into four steps, each a week or two apart. After testing whether Prerender pages could be cached in both S3 and minio, we slowly diverted traffic away from AWS S3 and towards minio. When the writes to S3 had been stopped completely, Prerender saved $200 a day on S3 API costs and signaled we were ready to start deleting data already cached in our Cassandra cluster.

However, the big reveal came at the end of this phase around June 24th. In the last four weeks, we moved most of the cache workload from AWS S3 to our own Cassandra cluster. The daily cost of AWS was reduced to $1.1K per day, projecting to 35K per month, and the new servers’ monthly recurring cost was estimated to be around 14K.

At this point, there were still some leftovers on S3 which cost around $60 per day and would completely die out naturally in a few weeks. Although we could have moved all the data out to cut it to zero immediately, it would have left us a one-time “money waste” of $5K to move data out of AWS.

Moving data around is where you’ll start running into huge bottlenecks. In the words of our new CTO (Zsolt Varga):

“ The true hidden price for AWS is coming from the traffic cost, they sell a reasonably priced storage, and it’s even free to upload it. But when you get it out, you pay an enormous cost.

Small startups often don’t calculate the traffic cost, even tho it can be 90% of their bill”

For example, if you are in the US West(Oregon) region, you have to shell out $0.080/GB whereas in the Asia Pacific (Seoul) region it bumps up to $0.135/GB.

In our case, it was easy around the $30k — $50k per month. By the end of phase two, we had reduced our total monthly server costs down by 41.2%.

Phase 3 — Implementation and Scaling (4 to 6 weeks)At this stage, the migration was well underway and was already saving Prerender a considerable amount of money. The only thing left to do was migrate all the other data onto the native servers.

This step involved moving all the Amazon RDS instances shard by shard. This was the most error-prone part of the whole process, but since a fair amount of the data had already been migrated, any hiccups or bottlenecks wouldn’t have brought the whole migration crashing down.

Here’s a big picture view of this last stage in the migration process:

We mirrored PostgreSQL shards storing cached_urls tables in CassandraWe switched service.prerender.io to Cloudflare load balancer to allow dynamic traffic distributionWe set up new EU private-recache serversWe keep performing stress tests to solve any performance issuesThe migration proved to be a resounding success in the end. Our monthly server fees dropped below our initial estimate of 40% to a full 80% by the time all the cached pages were redirected.

What We LearnedThere is a lot at stake in a server migration if things go wrong or fall behind schedule. That’s why we made sure to implement fail safes at each stage of the migration to make sure we could fall back if something were to go wrong. It’s also why we tested on a small scale before proceeding with the rest of the migration.

We avoided the dangers by carefully planning each stage of the migration, testing each stage of implementation before scaling, and making it easy to correct any errors should anything go wrong. That way, we could reap the benefits of saving on server fees while keeping any potential risks to a minimum.

What motivated you to work on the problem that Prerender solves?I was excited by the idea to work on a platform that helps to move the web forward.

You see, with Prerender our customers are rolling out user experience-focused websites and instead of concentrating on SEO they provide the best for their customers. In the past years anytime we built a new landing page we always used Wordpress just to get the best SEO out of it and reserved the power of SPA’s only for the non-indexed pages like the administration section. But now, I work with a company which helps to solve problems that held me back in the past ^.^

What technology stack do you use, and why did you choose this stack?We use Javascript everywhere, since we solve the “issues” caused by Javascript rendering we want to build as much expertise as possible in this field. But for the other parts, we are taking advantage of CloudFlare’s distributed system for fast response and global scalability. While our uptime guarantees are supported by Digital Ocean’s cloud platform. We also use a myriad of other SaaS providers to maximize our effectiveness.

What will the world look like once your company achieves its vision?When the question comes up “Can we use React for our new site?” the answer will be “For sure!”, because right now the marketing departments are always vetoing anything which can reduce the SEO ranking. I would say, rightfully. As for our customers even if they lose a 1% of effectiveness they would need to pump their ads budget with hundreds of thousands of dollars.

What does a typical day look like for you?Haha, lots of customer calls! As we aim to keep our dedicated team small and effective, I am more often than not in the onboarding calls with them. But it’s fun for me! I always loved to talk with customers, learn about their situation, and talk about solutions. This makes my job a lot easier, since we don’t have to come up with ideas, our customers are telling us everything we need to know. And I believe this is the best kind of situation, to be customer driven and my KPI is the number of happy customers.

Describe your computer hardware setupOh my, this would be worth an article itself. I am kinda a geek, and have 8 dedicated servers at home, while I am mostly working on my macbook for convenience. But when I get time for programming I spin up my “workstation” which runs Manjaro. But rarely when I get a bit of me time, I secretly turn on my windows pc for gaming. And at time of writing, I am surrounded by laptops, raspberries, and tablets as well.

Building machines and running downscaled tests is my late-night hobby.

Describe your computer software setupVSCode is a definitive solution for me, I am not really fond of any programming language and it gives me the freedom to just install an extension and write IDE supported code in seconds. Also, I had the luck to be in the beta group for CoPilot and it is a definitive game changer.

For source control GitHub is awesome, but I would never discount other solutions either. GitLab has become a really awesome tool in recent years.

Messaging, I think Slack still is the most widespread professional choice, and since it does its job, there is no reason to switch away from it. But recently I found a very interesting software called Spike and for the past 3 months, I have been using it as my de facto email client as it makes email conversations much easier.

Essential tools: Docker, there is no other way, it changed the industry for the best. I still remember the dark old days when we had to install dependencies and solve package conflicts…

But yeah, Kubernetes slowly is on the same level of adaptation.

Do you have any advice for software engineers who are just starting out?Don’t be afraid to talk with the customers. Throughout my career, the best software engineers were the ones who worked with the customer to solve their problems. Sometimes you can sack a half year of development time just by learning that you can solve the customer’s issue with a single line of code. I think the best engineers are creating solutions for real world problems.

Are you hiring and for what roles?Always! We always aim to only hire when we can ensure that our new colleagues will have a meaningful role and they make a definite contribution. But at the moment we have grown so much that we need to grow our team in every department. So, instead of listing just check our career page :D saas.group

Where can we go to learn more?Check out our site at prerender.io and if you are interested to have a call with me about prerendering and how it changes the web reach me in email at varga@prerender.io I am always happy to jump on a call and learn about your situation and use cases ^.^

Zsolt Varga is the General Manager of Prerender, a Google-recommended software tool used by more than 12,000 companies that allows search engines to better crawl and index Javascript websites.

[FJB] Weave Ignite github.com [graphic] Weave Ignite is an open source Virtual Mach...

FJB — 9/27/2022 7:06:20 AM

Weave Ignite

github.com

Weave Ignite is an open source Virtual Machine (VM) manager with a container UX and built-in GitOps management.

Combines Firecracker MicroVMs with Docker / OCI images to unify containers and VMs.

Works in a GitOps fashion and can manage VMs declaratively and automatically like Kubernetes and Terraform.

Ignite is fast and secure because of Firecracker. Firecracker is an open source KVM implementation from AWS that is optimised for high security, isolation, speed and low resource consumption. AWS uses it as the foundation for their serverless offerings (AWS Lambda and Fargate) that need to load nearly instantly while also keeping users isolated (multitenancy). Firecracker has proven to be able to run 4000 micro-VMs on the same host!

What is Ignite? Read the announcement blog post here: weave.works

Ignite makes Firecracker easy to use by adopting its developer experience from containers. With Ignite, you pick an OCI-compliant image (Docker image) that you want to run as a VM, and then just execute ignite run instead of docker run. There’s no need to use VM-specific tools to build .vdi, .vmdk, or .qcow2 images, just do a docker build from any base image you want (e.g. ubuntu:18.04 from Docker Hub), and add your preferred contents.

When you run your OCI image using ignite run, Firecracker will boot a new VM in about 125 milliseconds (!) for you using a default 4.19 Linux kernel. If you want to use some other kernel, just specify the --kernel-image flag, pointing to another OCI image containing a kernel at /boot/vmlinux, and optionally your preferred modules. Next, the kernel executes /sbin/init in the VM, and it all starts up. After this, Ignite connects the VMs to any CNI network, integrating with e.g. Weave Net.

Ignite is a declarative Firecracker microVM administration tool, similar to how Docker manages runC containers. Ignite runs VM from OCI images, spins VMs up/down at lightning speed, and can manage fleets of VMs efficiently using GitOps.

The idea is that Ignite makes Firecracker VMs look like Docker containers. Now we can deploy and manage full-blown VM systems just like e.g. Kubernetes workloads. The images used are OCI/Docker images, but instead of running them as containers, it executes their contents as a real VM with a dedicated kernel and /sbin/init as PID 1.

Networking is set up automatically, the VM gets the same IP as any container on the host would.

And Firecracker is fast! Building and starting VMs takes just some fraction of a second, or at most some seconds. With Ignite you can get started with Firecracker in no time!

Use-cases With Ignite, Firecracker is now much more accessible for end users, which means the ecosystem can achieve a next level of momentum due to the easy onboarding path thanks to the docker-like UX.

Although Firecracker was designed with serverless workloads in mind, it can equally well boot a normal Linux OS, like Ubuntu, Debian or CentOS, running an init system like systemd.

Having a super-fast way of spinning up a new VM, with a kernel of choice, running an init system like systemd allows running system-level applications like the kubelet, which need to “own” the full system.

Example use-cases:

Set up many secure VMs lightning fast. It's great for testing, CI and ephemeral workloads.

Launch and manage entire “app ready” stacks from Git because Ignite supports GitOps!

Run even legacy or special apps in lightweight VMs (eg for multi-tenancy, or using weird/edge kernels).

And - potentially - we can run a cloud of VMs ‘anywhere’ using Kubernetes for orchestration, Ignite for virtualization, GitOps for management, and supporting cloud native tools and APIs.

Scope Ignite is different from Kata Containers or gVisor. They don’t let you run real VMs, but only wrap a container in a VM layer providing some kind of security boundary (or sandbox).

Ignite on the other hand lets you run a full-blown VM, easily and super-fast, but with the familiar container UX. This means you can “move down one layer” and start managing your fleet of VMs powering e.g. a Kubernetes cluster, but still package your VMs like containers.

Installing Please check out the Releases Page.

How to install Ignite is covered in docs/installation.md or on Read the Docs.

Guidance on Cloud Providers' instances that can run Ignite is covered in docs/cloudprovider.md.

Getting Started WARNING: In it's v0.X series, Ignite is in alpha, which means that it might change in backwards-incompatible ways.

Note: At the moment ignite and ignited need root privileges on the host to operate due to certain operations (e.g. mount). This will change in the future.

# Let's run the weaveworks/ignite-ubuntu OCI image as a VM # Use 2 vCPUs and 1GB of RAM, enable automatic SSH access and name it my-vm ignite run weaveworks/ignite-ubuntu \     --cpus 2 \     --memory 1GB \     --ssh \     --name my-vm  # List running VMs ignite ps  # List Docker (OCI) and kernel images imported into Ignite ignite images ignite kernels  # Get the boot logs of the VM ignite logs my-vm  # SSH into the VM ignite ssh my-vm  # Inside the VM you can check that the kernel version is different, and the IP address came from the container # Also the memory is limited to what you specify, as well as the vCPUs > uname -a > ip addr > free -m > cat /proc/cpuinfo  # Rebooting the VM tells Firecracker to shut it down > reboot  # Cleanup ignite rm my-vm

For a walkthrough of how to use Ignite, go to docs/usage.md.

Getting Started the GitOps way Ignite is a “GitOps-first” project, GitOps is supported out of the box using the ignited gitops command. Previously this was integrated as ignite gitops, but this functionality has now moved to ignited, Ignite's upcoming daemon binary.

In Git you declaratively store the desired state of a set of VMs you want to manage. ignited gitops reconciles the state from Git, and applies the desired changes as state is updated in the repo. It also commits and pushes any local changes/additions to the managed VMs back to the repository.

This can then be automated, tracked for correctness, and managed at scale - just some of the benefits of GitOps.

The workflow is simply this:

Run ignited gitops [repo], where repo is an SSH url to your Git repo

Create a file with the VM specification, specifying how much vCPUs, RAM, disk, etc. you’d like for the VM

Run git push and see your VM start on the host

See it in action! (Note: The screencast is from an older version which differs somewhat)

[FJB] so awesome Diving into GCC internals Binaries and processesLooking at the gen...

FJB — 6/13/2022 11:54:24 PM

so awesome

Diving into GCC internals

Binaries and processes

Looking at the generated assembler

Inside cc1

What’s in the GCC source tree?

[FJB] Miracle Drug Shows 100% Remission For All Cancer Patients In Drug Trial

FJB — 6/7/2022 9:29:44 PM

[FJB] hpcwire.com Nvidia R&D Chief on How AI is Improving Chip Design ...

FJB — 4/20/2022 7:03:09 AM

hpcwire.com

Nvidia R&D Chief on How AI is Improving Chip Design
By John Russell

8-10 minutes

Getting a glimpse into Nvidia’s R&D has become a regular feature of the spring GTC conference with Bill Dally, chief scientist and senior vice president of research, providing an overview of Nvidia’s R&D organization and a few details on current priorities. This year, Dally focused mostly on AI tools that Nvidia is both developing and using in-house to improve its own products – a neat reverse sales pitch if you will. Nvidia has, for example begun using AI to effectively improve and speed GPU design.

Bill Dally of Nvidia in his home ‘workshop’ “We’re a group of about 300 people that tries to look ahead of where we are with products at Nvidia,” described Dally in his talk this year. “We’re sort of the high beams trying to illuminate things in the far distance. We’re loosely organized into two halves. The supply half delivers technology that supplies GPUs. It makes GPUs themselves better, ranging from circuits, to VLSI design methodologies, architecture networks, programming systems, and storage systems that go into GPUs and GPUs systems.”

“The demand side of Nvidia research tries to drive demand for Nvidia products by developing software systems and techniques that need GPUs to run well. We have three different graphics research groups, because we’re constantly pushing the state of the art in computer graphics. We have five different AI groups, because using GPUs to run AI is currently a huge thing and getting bigger. We also have groups doing robotics and autonomous vehicles. And we have a number of geographically ordered oriented labs like our Toronto and Tel Aviv AI labs,” he said.

Occasionally, Nvidia launches a Moonshot effort pulling from several groups – one of these, for example, produced Nvidia’s real-time ray tracing technology.

As always, there was overlap with Dally’s prior-year talk – but there was also new information. The size of the group has certainly grown from around 175 in 2019. Not surprisingly, efforts supporting autonomous driving systems and robotics have intensified. Roughly a year ago, Nvidia recruited Marco Pavone from Stanford University to lead its new autonomous vehicle research group, said Dally. He didn’t say much about CPU design efforts, which are no doubt also intensifying.

Presented here are small portions of Dally’s comments (lightly edited) on Nvidia’s growing use of AI in designing chips along a with a few supporting slides.

1 Mapping Voltage Drop

“It’s natural as an expert in AI that we would want to take that AI and use it to design better chips. We do this in a couple of different ways. The first and most obvious way is we can take existing computer-aided design tools that we have [and incorporate AI]. For example, we have one that takes a map of where power is used in our GPUs, and predicts how far the voltage grid drops – what’s called IR drop for current times resistance drop. Running this on a conventional CAD tool takes three hours,” noted Dally.

“Because it’s an iterative process, that becomes very problematic for us. What we’d like to do instead is train an AI model to take the same data; we do this over a bunch of designs, and then we can basically feed in the power map. The [resulting] inference time is just three seconds. Of course, it’s 18 minutes if you include the time for feature extraction. And we can get very quick results. A similar thing in this case, rather than using a convolutional neural network, we use a graph neural network, and we do this to estimate how often different nodes in the circuit switch, and this actually drives the power input to the previous example. And again, we’re able to get very accurate power estimations much more quickly than with conventional tools and in a tiny fraction of the time,” said Dally.

2 Predicting Parasitics

“One that I particularly like – having spent a fair amount of time a number of years ago as a circuit designer – is predicting parasitics with graph neural networks. It used to be that circuit design was a very iterative process where you would draw a schematic, much like this picture on the left here with the two transistors. But you wouldn’t know how it would perform until after a layout designer took that schematic and did the layout, extracted the parasitics, and only then could you run the circuit simulations and find out you’re not meeting some specifications,” noted Dally.

“You’d go back and modify your schematic [and go through] the layout designer again, a very long and iterative and inhuman labor-intensive process. Now what we can do is train neural networks to predict what the parasitics are going to be without having to do layout. So, the circuit designer can iterate very quickly without having that manual step of the layout in the loop. And the plot here shows we get very accurate predictions of these parasitics compared to the ground truth.”

3 Place and Routing Challenges

“We can also predict routing congestion; this is critical in the layout of our chips. The normal process is we would have to take a net list, run through the place and route process, which can be quite time consuming often taking days. And only then we would get the actual congestion, finding out that our initial placement is not adequate. We need to refactor it and place the macros differently to avoid these red areas (slide below), which is where there’s too many wires trying to go through a given area, sort of a traffic jam for bits. What we can do instead now is without having to run the place and route, we can take these net lists and using a graph neural network basically predict where the congestion is going to be and get fairly accurate. It’s not perfect, but it shows the areas where there are concerns, we can then act on that and do these iterations very quickly without the need to do a full place and route,” he said.

4 Automating Standard Cell Migration

“Now those [approaches] are all sort of using AI to critique a design that’s been done by humans. What’s even more exciting is using AI to actually do the design. I’ll give you two examples of that. The first is a system we have called NVCell, which uses a combination of simulated annealing and reinforcement learning to basically design our standard cell library. So each time we get a new technology, say we’re moving from a seven nanometer technology to a five nanometer technology, we have a library of cells. A cell is something like an AND gate and OR gate, a full adder. We’ve got actually many thoundands of these cells that have to be redesigned in the new technology with a very complex set of design rules,” said Dally.

“We basically do this using reinforcement learning to place the transistors. But then more importantly, after they’re placed, there are usually a bunch of design rule errors, and it goes through almost like a video game. In fact, this is what reinforcement learning is good at. One of the great examples is using reinforcement learning for Atari video games. So this is like an Atari video game, but it’s a video game for fixing design rule errors in a standard cell. By going through and fixing these design rule errors with reinforcement learning, we’re able to basically complete the design of our standard cells. What you see (slide) is that the 92 percent of the cell library was able to be done by this tool with no design rule or electrical rule errors. And 12 percent of them are smaller than the human design cells, and in general, over the cell complexity, [this tool] does as well or better than the human design cells,” he said.

“This does two things for us. One is it’s a huge labor savings. It’s a group on the order of 10 people will take the better part of a year to port a new technology library. Now we can do it with a couple of GPUs running for a few days. Then the humans can work on those 8 percent of the cells that didn’t get done automatically. And in many cases, we wind up with a better design as well. So it’s labor savings and better than human design.”

There was a good deal more to Dally’s talk, all of it a kind of high-speed dash through a variety of Nvidia’s R&D efforts. If you’re interested, here is HPCwire’s coverage of two previous Dally R&D talks – 2019, 2021 – for a rear-view mirror into work that may begin appearing in products. As a rule, Nvidia’s R&D is very product-focused rather than basic science. You’ll note his description of the R&D mission and organization hasn’t changed much but the topics are different.

[retrodynamic] State of the Art Novel InFlow Tech: ·1-Gearturbine Reaction Turbine Rotary Turbo...

retrodynamic — 4/17/2022 9:58:48 PM

State of the Art Novel InFlow Tech: ·1-Gearturbine Reaction Turbine Rotary Turbo, ·2-Imploturbocompressor Impulse Turbine 1 Compression Step.

·1-Gearturbine: Reaction Turbine, ·Rotary-Turbo, Similar System of the Aeolipilie ·Heron Steam Device from 10-70 AD, ·With Retrodynamic = DextroGiro/RPM VS LevoGiro/InFlow, + ·Ying Yang Circular Power Type, ·Non Waste Parasitic Power Looses Type, ·8-X,Y Thermodynamic Cycle Way Steps, Patent: #197187 / IMPI - MX.

·2-Imploturbocompressor: Impulse Turbine, ·Implo-Ducted, One Moving Part System Excellence Design, · InFlow Goes from Macro-Flow to Micro-Flow by Implosion/And Inverse, ·One Compression Step, ·Circular Dynamic Motion. Implosion Way Type, ·Same Nature of a Hurricane Satellite View.

stateoftheartnovelinflowtech.blogspot.com

https://padlet.com/gearturbine/un2slbar3s94

https://www.behance.net/gearturbina61a

[FJB] Writing a Simple Operating System — from Scratch cs.bham.ac.uk

FJB — 3/25/2022 5:18:32 PM

[FJB] Lanai, the mystery CPU architecture in LLVM. Disclaimer: I have had access to...

FJB — 3/21/2022 8:44:32 PM

Lanai, the mystery CPU architecture in LLVM.

Disclaimer: I have had access to some confidential information about some of the matter discussed in this page. However, everything written here is derived form publicly available sources, and references to these sources are also provided.

https://q3k.org/lanai.html
https://q3k.org/lanai.html

Some of my recent long-term projects revolve around a little known CPU architecture called 'Lanai'. Unsurprisingly, very few people have heard of it, and even their Googling skills don't come in handy. This page is a short summary of what I know, and should serve as a reference for future questions.

Myricom & the origins of Lanai Myricom is a hardware company founded in 1994. One of their early products was a networking interface card family and protocol, Myrinet. I don't know much about it, other than it did some funky stuff with wormhole routing.

As part of their network interface card design, they introduced data plane programmability with the help of a small RISC core they named LANai. It originally ran at 33MHz, the speed of the PCI bus on which the cards were operating. These cores were quite well documented on the Myricom website, seemingly with the end-user programmability being a selling point of their devices.

It's worth noting that multiple versions of LANai/Lanai have been released. The last publicly documented version on the old Myricom website is Lanai3/4. Apart from the documentation, sources for a gcc/binutils fork exist to this day on Myricom's Github.

At some point, however, Myricom stopped publicly documenting the programmability of their network cards, but documentation/SDK was still available on request. Some papers and research websites actually contain tutorials on how to get running with the newest versions of the SDK at the time, and even document the differences between the last documented Lanai3/4 version and newer releases of the architecture/core.

This closing down of the Lanai core documentation by Myricom didn't mean they stopped using it in their subsequent cards. The core made its way into their Ethernet offerings (after Myrinet basically died), like their 10GbE network cards. You can easily find these 10G cards on eBay, and they even have the word 'Lanai' written on their main ASIC package. Even more interestingly, Lanai binaries are shipped with Linux firmware packages, and can be chucked straight into a Lanai disassembler (eg. the Myricom binutils fork's objdump).

Technical summary of Lanai3/4

32 registers, most of them general purpose, with special treatment for R0 (all zeroes), R1 (all ones), R2 (the program counter), R3 (status register), and some registers allocated for mode/context switching.
4-stage RISC-style pipeline: Calculate Address, Fetch, Compute, Memory
Delay slot based pipeline hazard resolution
No multiplication, no division. It's meant to route packets, not crunch numbers.
The world's best instruction mnemonic: PUNT, to switch between user and system contexts.

Here's a sample of Lanai assembly:

000000f8 <main>:       f8: 92 93 ff fc   st      %fp, [--%sp]       fc: 02 90 00 08   add     %sp, 0x8, %fp      100: 22 10 00 08   sub     %sp, 0x8, %sp      104: 51 80 00 00   or      %r0, 0x0, %r3      108: 04 81 40 01   mov     0x40010000, %r9      10c: 54 a4 08 0c   or      %r9, 0x80c, %r9      110: 06 01 11 11   mov     0x11110000, %r12      114: 56 30 11 11   or      %r12, 0x1111, %r12      118: 96 26 ff f4   st      %r12, -12[%r9]      11c: 96 26 ff f8   st      %r12, -8[%r9]      120: 86 26 13 f8   ld      5112[%r9], %r12  00000124 <.LBB3_1>:      124: 46 8d 00 00   and     %r3, 0xffff, %r13      128: 96 a4 00 00   st      %r13, 0[%r9]      12c: 01 8c 00 01   add     %r3, 0x1, %r3      130: e0 00 01 24   bt      0x124 <.LBB3_1>      134: 96 24 00 00   st      %r12, 0[%r9]

The `add`/`sub`/`or` instruction have their destination on the right hand side. `st` and `ld` are memory store and load instructions respectively. Note the lack of 32-bit immediate load (instead a `mov` and `or` instruction are used in tandem). That `mov` instruction isn't real, either - it's a pseudo instruction for an `add 0, 0x40010000, %r9`. Also note the branch delay slot at address 134 (this instruction gets executed even if the branch at 130 is taken).

The ISA is quite boring, and in my opinion that's a good thing. It makes core implementations easy and fast, and it generally feels like one of the RISC-iest cores I've dealt with. The only truly interesting thing about it is its' dual-context execution system, but that unfortunately becomes irrelevant at some point, as we'll see later.

Google & the Lanai team In the early 2010s, things weren't going great at Myricom. Due to financial and leadership difficulties, some of their products got canceled, and in 2013, core Myricom engineers were bought out by Google, and they transferred the Lanai intellectual property rights with them. The company still limps on, seemingly targeting the network security and fintech markets, and even continuing to market their networking gear as programmable, but Lanai is nowehere to be seen in their new designs.

So what has Google done with the Lanai engineers and technology? The only thing we know is that in 2016 Google implemented and upstreamed a Lanai target in LLVM, and that it was to be used internally at Google. What is it used for? Only Google knows, and Google isn't saying.

The LLVM backend targets Lanai11. This is quite a few numbers higher than the last publicly documented Lanai3/4, and there's quite a few differences between them:

No more dual-context operation, no more PUNT instruction. The compiler/programmer can now make use of nearly all registers from r4 to r31.
No more dual-ALU (R-R-R) instructions. This was obviously slow, and was probably a combinatorial bottleneck in newer microarchitectural implementations.
Slightly different delay slot semantics, pointing at a new microarchitecture (likely having stepped away from a classic RISC pipeline into something more modern).
New additional instruction format and set of accompanying instructions: SPLS (special part-word load/store), SLI (special load immediate), and Special Instruction (containing amongst others popcount, of course).

Lanai Necromancy As you can tell by this page, this architecture intrigued me. The fact that it's an LLVM target shipped with nearly every LLVM distribution while no-one has access to hardware which runs the emitted code is just so spicy. Apart from writing this page, I have a few other Lanai-related projects, and I'd like to introduce them here:

I'm porting Rust to Lanai11. I have a working prototype, which required submitting some patches to upstream LLVM to deal with IR emitted by rustc. This has been upstreamed. My rustc patches are pending on...
I'm implementing LLD support for Lanai. Google (in the LLVM mailing list posts) mentions they use a binutils ld, forked off from the Myricom binutils fork. I've instead opted to implement an LLD backend for Lanai, which currently only supports the simplest relocations. I haven't yet submitted a public LLVM change request for this, but this is on my shortlist of things to do. I have to first talk to the LLVM/Google folks on the maintenance plan for this.
I've implemented a simple Lanai11 core in Bluespec, as part of my qfc monorepo. 3-stage pipeline (merged addr/fetch stages), in-order. It's my first bit of serious Bluespec code, so it's not very good. I plan on implementing a better core at some point.
I've implemented a small Lanai-based microcontroller, qf105, which is due to be manufactured in 130nm as part of the OpenMPW5 shuttle. Which is, notably, sponsored by Google :).

If you're interested in following or joining these efforts, hop on to ##q3k on libera.chat.

In addition to my effort piecing together information about Lanai and making use of it for my own needs, the TrueBit project also used it as a base for their smart contract system (in which they implemented a Lanai interpreter in Solidity).

Documentation Useful resources, in no particular oder:

Original Lanai3/4 docs from Myricom's website, archived.
Myrinet tutorial by James Otto, archived.
A Myrinet Firmware development experience by Marc Herbert.
Lanai per-generation ISA differences, as shown by GCC architecture/machine options.

[FJB] Security Engineering Lecture 1: Who is the Opponent? [youtube video]

FJB — 1/19/2022 6:47:06 PM

[FJB] gist.github.com How to setup a practically free CDN I've been using Backblaze ...

FJB — 1/15/2022 4:15:04 PM

gist.github.com

How to setup a practically free CDN I've been using Backblaze for a while now as my online backup service. I have used a few others in the past. None were particularly satisfactory until Backblaze came along.

It was - still is - keenly priced at a flat $5 (£4) per month for unlimited backup (I've currently got just under half a terabyte backed-up). It has a fast, reliable client. The company itself is transparent about their operations and generous with their knowledge sharing. To me, this says they understand their customers well. I've never had reliability problems and everything about the outfit exudes a sense of simple, quick, solid quality. The service has even saved the day on a couple of occasions where I've lost files.

Safe to say, I'm a happy customer. If you're not already using Backblaze, I highly recommend you do.

Taking on the big boys with B2 So when Backblaze announced they were getting into the cloud storage business, taking on the likes of Amazon S3, Microsoft Azure, and Google Cloud, I paid attention. Even if the cost were the same, or a little bit more, I'd be interested because I like the company. I like their product, and I like their style.

What I wasn't expecting was for them to be cheaper. Much cheaper. How about 440% cheaper than S3 per GB? Don't believe me? Take a look. Remarkable.

What's more, they offer a generous free tier of 10 GB free storage and 1 GB free download per day.

If it were any other company, I might think they're a bunch of clowns trying it on. But I know from my own experience and following their journey, they're genuine innovators and good people.

Using B2 B2 is pretty simple. You can use their web UI, which is decent. Or you can use Cyberduck, which is what I use, is free, and of high quality. There is also a command-line tool and a number of other integrated tools. There is also a web API, of course.

Setting up a vanity URL You can set up a "vanity" URL for your public B2 files. Do it for free using CloudFlare. There's a PDF [1.3 MB] documenting how.

Using CloudFlare CDN to cache B2 hosted files You can also configure CloudFlare to aggressively cache assets served by your B2 service. It is not immediately obvious how to do this, and took a bit of poking around to set up correctly.

By default, B2 serves with cache-invalidating headers: cache-control:max-age=0, no-cache, no-store, which causes CloudFlare to skip caching of assets. You can see this happening by looking for the cf-cache-status:MISS header.

To work around this problem, you can use CloudFlare's PageRules specifying an "Edge cache expire TTL". I won't explain what that means here as it is covered in-depth on the CloudFlare blog.

So, to cache your B2 assets, you need to create a PageRule that includes all files on your B2 domain. For example:

files.silversuit.net/* You then need to add your cache settings. I have Cache Level set to Cache Everything; Browser Cache TTL set to a year; Edge Cache TTL set to 7 days. I'm caching aggressively here, but you can tweak these settings to suit. Here's a screenshot:

Screenshot showing PageRules settings To check that it's working correctly, use DevTools to look for the cf-cache-status:HIT header:

Screenshot showing a CloudFlare cache hit Wrapping up So, with that, you're making use of already very inexpensive B2 storage coupled with CloudFlare's free CDN to serve your assets almost entirely for free. And it's not like these are rinky-dink services that are going to fall over regularly; these are both high-quality, reputable companies.

What a time to be alive, eh?

[FJB] NASM Assembly Language Tutorials - asmtutor.com ...

FJB — 1/3/2022 7:26:11 PM

NASM Assembly Language Tutorials -
asmtutor.com
asmtutor.com

[FJB] Data Structure Visualizations cs.usfca.edu

FJB — 7/7/2021 5:59:45 PM

[FJB] The 'most complicated machine humans have built' keeps US technology a de...

FJB — 7/6/2021 5:45:27 PM

The 'most complicated machine humans have built' keeps US technology a decade ahead of China
John Sexton

hotair.com

I’ve written about this before but yesterday the NY Times published an interesting piece on the EUV lithography machines produced by ASML and how those machines really determine who can manufacture cutting edge microchips.

As you probably know, there’s a concept called Moore’s Law which suggests that the complexity of microchips doubles every two years while the cost of the chips is cut in half. And for the most part that has held true since the first CPUs were introduced in the 1970s.

But cramming more and more transistors into the same physical space gets harder to do over time. With each successive generation of chips, the number of transistors packed into a square millimeter has to climb. Actually making that happen turns out to be massively difficult. In fact, it required expertise from different companies around the world to allow for the creation of the world’s first EUV lithography machines. The machine itself is about the size and shape of a bus and costs $150 million dollars each.

Inside are a series of mirrors which reflect ultraviolent light through an image of the chip, shrinking it down so many copies can be printed onto a single silicon wafer. ASML partnered with German optical company Zeiss to produce the high end optics for the machines. But it turns out that even the best mirrors aren’t that reflective to the ultraviolet wavelengths needed to produce the small traces on the latest chips. So the light source has to be very bright to compensate. In the end, ASML settled on a design which sprays tiny droplets of molten tin. Those droplets are then hit with a powerful laser which instantly turns them into a plasma that releases a lot of ultraviolet light.

To say it’s a complicated system is underselling it substantially. An IBM senior VP calls it the most complicated machine ever built by humans. ASML has only made about 100 of them and can only make a maximum of about 50 of them in a year. But thanks to the Trump administration, China can’t buy one.

The tool, which took decades to develop and was introduced for high-volume manufacturing in 2017, costs more than $150 million. Shipping it to customers requires 40 shipping containers, 20 trucks and three Boeing 747s.

The complex machine is widely acknowledged as necessary for making the most advanced chips, an ability with geopolitical implications. The Trump administration successfully lobbied the Dutch government to block shipments of such a machine to China in 2019, and the Biden administration has shown no signs of reversing that stance.

Manufacturers can’t produce leading-edge chips without the system, and “it is only made by the Dutch firm ASML,” said Will Hunt, a research analyst at Georgetown University’s Center for Security and Emerging Technology, which has concluded that it would take China at least a decade to build its own similar equipment. “From China’s perspective, that is a frustrating thing.”…

Since ASML introduced its commercial EUV model in 2017, customers have bought about 100 of them. Buyers include Samsung and TSMC, the biggest service producing chips designed by other companies. TSMC uses the tool to make the processors designed by Apple for its latest iPhones. Intel and IBM have said EUV is crucial to their plans.

“It’s definitely the most complicated machine humans have built,” said Darío Gil, a senior vice president at IBM.

It would probably take a decade and a trillion dollars for China to replicate the European, Japanese and American supply chain that produces the parts for the ASML EUV lithography machine. That’s a long time and by the time they got it done the free would would have moved on to something even more advanced.

But once place that does have these machines is the world’s leading chipmaker, a company called TSMC which stands for Taiwan Semiconductor Manufacturing Company Co. So if you’re wondering why China is so hot to reunite Taiwan with the mainland, one reason may be that in taking over the island they would effectively seize control of the latest ASML machines which they can’t buy and can’t produce on their own. It would be the greatest theft of advanced technology in China’s history. If China wants its technology to catch up with the rest of the world, an invasion of Taiwan is probably their best bet.

Of course invading Taiwan would probably put an end to selling new EUV machines to TSMC, but the disruption of potentially having TSMC under Chinese control would potentially set back the rest of the world’s manufacturing by several years. China might not be able to catch up completely but they could jump ahead several years and set the US back at the same time. It’s one reason the US has been looking into being less dependent on places like Taiwan for our high tech manufacturing as we move forward.

Update: This primer on EUV lithography from Zeiss notes that a single image printed by the optical system contains about a terrapixel of information. That’s equivalent to 2.4 million times the number of pixels in an HDTV.

One more mind-blowing stat. If you expanded an EUV mirror to cover the entire size of Germany the largest bump on the surface would be 100 micrometers tall. That’s how perfect these optics that produce the chips in a modern iPhone are.

[FJB] WRITING ARM ASSEMBLY -- THIS COULD GET ME TO BUY A MAC... eclecticlight.co ...

FJB — 6/16/2021 2:10:59 PM

WRITING ARM ASSEMBLY -- THIS COULD GET ME TO BUY A MAC...

eclecticlight.co

Code in Assembly for Apple Silicon with the AsmAttic app

Learning a little assembly language is not only good for the soul, but it has value for anyone wanting to deepen their understanding of a processor, those who want to read disassembled code such as security researchers, and anyone writing code in a higher-level language such as Objective-C or Swift. Although there are several good books about ARM assembly (see references), using it in Xcode apps is not well documented. Apple’s developer information is most helpful to those who already write assembly and are accustomed to its quirks.

This article is the first of what I hope will be a series to open up access to assembly coding for Apple Silicon Macs. Here I take you through building a simple app which wraps itself around four lines of ARM64 assembly code, and provides a platform for subsequent articles. To work through this, you’ll need an M1 Mac and Xcode 12.5 (free from the App Store), and I assume that you’re sufficiently familiar with that and Swift to be able to build a basic app in AppKit or similar.

The complete Xcode project is available here: asmattic

Start by creating a new project for a macOS app, which I’ve named AsmAttic. Set its Interface and Life Cycle to support your favourite model. In my case, that’s a conventional Storyboard with an AppKit App Delegate and Swift as its language. You’re welcome to use SwiftUI or anything else which you find straightforward.

In its Project Build Settings, set it to build the Active Architecture only for both debug and release versions, so that Xcode will only make ARM versions of the app. If you want to support Intel, you’ll need to add conditionals to ensure that the assembly is only built for and called by the ARM version.

Build your app a little interface window, here with three numeric input boxes, and a scrolling text output view, so that it can take three floating point numbers as input, and write a string containing the results. Add real code to perform the compiled equivalent of what you’re going to code in assembly, a double multiply and add.

My primary purpose in exploring ARM assembly is to look in greater detail at its floating point arithmetic. The instructions which I’m most interested in merge two arithmetic operations, multiply and add. They take three doubles, a, b and c, and calculate the result of
(a * b) + c
They’re of particular interest to me because they reduce error compared with two separate operations. So that’s what this initial version of AsmAttic is going to perform in both Swift and assembly.

At this stage, wire up the window with code which performs that using Swift (see the completed code below for one solution). Test the app to ensure that it works without calling any assembly routines.

When you’re happy that’s working correctly, add a New File, selecting the Assembly type, and naming it asmmath.s. The code that contains is short and sweet:
.global _multadd
.align 4

_multadd:
STR LR, [SP, #-16]!
FMADD D0, D0, D1, D2
LDR LR, [SP], #16
RET

That stores a set of registers, performs the FMADD operation on the three doubles, leaves the result in D0, restores the registers, and returns.

To be able to access that from Swift, you then need a C header file, asmmath.h, which contains just the following:
#ifndef asmmath_h
#define asmmath_h
extern double multadd(double, double, double);
#endif /* asmmath_h */
As with the other files here, ensure this is added to the target of the project.

In theory, Xcode should automatically generate a bridging header to enable your Swift code to call that assembly routine. In practice, I’ve not seen that happen, and have had to create that manually. To do that, add another Header file, this time named AsmAttic-Bridging-Header.h. Inside that, the key line is:
#include "asmmath.h"
which bridges between Swift and the C header, which in turn wraps the _multadd routine in assembly language.

The final step is to tell Xcode to use that bridging header in the project’s Build Settings. Locate within those the Swift Compiler – General section, and add as the location for the bridging header the path to your file relative to the project file, typically something like
AsmAttic/AsmAttic-Bridging-Header.h
If you get that wrong, Xcode will complain that it can’t find the bridging header and builds will fail with that error.

Go back to your Swift code to handle the button press, and call the assembly routine using code such as
let theRes2 = multadd(theA.doubleValue, theB.doubleValue, theC.doubleValue)
so you can print theRes2 as its result in the output text.

My final code for the ViewController reads:

class ViewController: NSViewController { @IBOutlet weak var no1Text: NSTextField! @IBOutlet weak var no1Formatter: NumberFormatter! @IBOutlet weak var no2Text: NSTextField! @IBOutlet weak var no2Formatter: NumberFormatter! @IBOutlet weak var no3Text: NSTextField! @IBOutlet weak var no3Formatter: NumberFormatter! @IBOutlet var outputText: NSTextView! override func viewDidLoad() { super.viewDidLoad() // Do any additional setup after loading the view. } override var representedObject: Any? { didSet { // Update the view, if already loaded. } } @IBAction func goButton(_ sender: Any) { if let theA = self.no1Formatter.number(from: self.no1Text.stringValue) { if let theB = self.no2Formatter.number(from: self.no2Text.stringValue) { if let theC = self.no3Formatter.number(from: self.no3Text.stringValue) { let theRes1 = theA.doubleValue * theB.doubleValue + theC.doubleValue let theRes2 = multadd(theA.doubleValue, theB.doubleValue, theC.doubleValue) self.outputText.string = "In Swift \(theRes1), by assembler \(theRes2)\n" } } } } } Your app should now let you set the three variables, calculate the result both using Swift and the FMADD operation, and write the result to the output view.

Passing the three doubles to the assembly language routine and passing the result back relies on the calling convention, which passes the three values in registers D0 to D2, and returns the result in D0. In the next article I’ll look at those calling conventions, which are so crucial to success in assembly language.

References

Stephen Smith (2020) Programming with 64-Bit ARM Assembly Language, Apress, ISBN 978 1 4842 5880 4.
Daniel Kusswurm (2020) Modern Arm Assembly Language Programming, Apress, ISBN 978 1 4842 6266 5.

[FJB] Beads Language Home site Home ...

FJB — 5/27/2021 12:29:44 PM

Beads Language Home site

Home
Projects
Blog
Contact
The beads project

About

What I Do

Now is the time for a new programming paradigm. Previous generations of languages were called imperative, object-oriented, and then functional. The next generation of languages is now possible: Declarative languages, which have almost no bugs, and offer a 10:1 reduction in total lifecycle cost. For many graphical interactive or client/server applications, you can replace the entire development stack with one relatively simple tool.

The Beads language compiler is now available, free. It supports both Macintosh and Windows OS (sorry, no Linux yet). Please download the SDK, unzip it, and read the READ ME file to get started. There is a YouTube video showing how to get started for Macintosh or Windows. Linux development can be done using Wine to create a virtual Windows under Linux.

Download Compiler & SDK

Visit our community pages on Discord

See examples on GitHub

Watch YouTube videos on Beads

The next generation computer language and toolchain, code-named "Beads", has the following goals:

1) Provide an alternative to Excel for business modeling and automation.
2) Make it easier for programs to be improved by someone other than the original author.
3) Provide a system that protects against programmer errors to the extent possible
4) Offer a notation that is independent of hardware and operating systems, so that programs will last for decades.

EXCEL is clumsy and unreliableMillions of businesses use Excel every day, but it is clumsy and difficult to audit. Beads offers businesses a way to automate business processes without a large investment.

Beads can build a complex product using one simple language.Never in history have programmers had to work in so many languages and frameworks at once. A typical project today might use HTML, CSS, Javascript, Apache, MySQL, PHP, and perhaps multiple frameworks like jQuery or React. This is a complex set of tools that is costly and cumbersome to use. In Beads, you work in one language that is simple and direct.

beads works both forwards and backwardsAuthoring a program is not where the productivity problem in software lies. The real drawback of current tools is that when you look at the screen (the output), and want to go backwards into the source code to make some change, it is very difficult and time consuming. The majority of time in conventional programming is spent in the backwards process euphemistically called debugging. Beads has a unique ability to make the reverse linkage more direct, so that it is easier to figure out where in the source code a particular problem occurs.

Beads includes a databaseIn many languages when it comes time to manipulate and store data you use an external database. Beads' internal data structures, which resemble the graph database as exemplified by Neo4J, are so powerful and flexible that you don't normally use an external database system. This dramatically simplifies the programming task, as working with databases always makes things more complex.

Beads is robustIn many languages the slightest error in input data can cause a program to seriously malfunction. Beads has special rules of arithmetic and a robust mathematical model, that makes it extremely difficult to have a serious malfunction.

Reality is merely an illusion, albeit a very persistent one. -- Albert Einstein

[FJB] Cerebras launches new AI supercomputing processor with 2.6 trillion transistors ...

FJB — 4/20/2021 4:35:54 PM

Cerebras launches new AI supercomputing processor with 2.6 trillion transistors

Dean Takahashi
venturebeat.com /2021/04/20/cerebras-systems-launches-new-ai-supercomputing-processor-with-2-6-trillion-transistors/
4/20/2021

Join Transform 2021 this July 12-16. Register fo r the AI event of the year.

Cerebras Systems has unveiled its new Wafer Scale Engine 2 processor with a record-setting 2.6 trillion transistors and 850,000 AI-optimized cores. It’s built for supercomputing tasks, and it’s the second time since 2019 that Los Altos, California-based Cerebras has unveiled a chip that is basically an entire wafer.

Chipmakers normally slice a wafer from a 12-inch-diameter ingot of silicon to process in a chip factory. Once processed, the wafer is sliced into hundreds of separate chips that can be used in electronic hardware.

But Cerebras, started by SeaMicro founder Andrew Feldman, takes that wafer and makes a single, massive chip out of it. Each piece of the chip, dubbed a core, is interconnected in a sophisticated way to other cores. The interconnections are designed to keep all the cores functioning at high speeds so the transistors can work together as one.

Twice as good as the CS-1

Above: Comparing the CS-1 to the biggest GPU.

Image Credit: Cerebras

In 2019, Cerebras could fit 400,000 cores and 1.2 billion transistors on a wafer chip, the CS-1. It was built with a 16-nanometer manufacturing process. But the new chip is built with a high-end 7-nanometer process, meaning the width between circuits is seven billionths of a meter. With such miniaturization, Cerebras can cram a lot more transistors in the same 12-inch wafer, Feldman said. It cuts that circular wafer into a square that is eight inches by eight inches, and ships the device in that form.

“We have 123 times more cores and 1,000 times more memory on chip and 12,000 times more memory bandwidth and 45,000 times more fabric bandwidth,” Feldman said in an interview with VentureBeat. “We were aggressive on scaling geometry, and we made a set of microarchitecture improvements.”

Now Cerebras’ WSE-2 chip has more than twice as many cores and transistors. By comparison the largest graphics processing unit (GPU) has only 54 billion transistors — 2.55 trillion fewer transistors than the WSE-2. The WSE-2 also has 123 times more cores and 1,000 times more high performance on-chip high memory than GPU competitors. Many of the Cerebras cores are redundant in case one part fails.

“This is a great achievement, especially when considering that the world’s third largest chip is 2.55 trillion transistors smaller than the WSE-2,” said Linley Gwennap, principal analyst at The Linley Group, in a statement.

Feldman half-joked that this should prove that Cerebras is not a one-trick pony.

“What this avoids is all the complexity of trying to tie together lots of little things,” Feldman said. “When you have to build a cluster of GPUs, you have to spread your model across multiple nodes. You have to deal with device memory sizes and memory bandwidth constraints and communication and synchronization overheads.”

The CS-2’s specs

Above: TSMC put the CS-1 in a chip museum.

Image Credit: Cerebras

The WSE-2 will power the Cerebras CS-2, the industry’s fastest AI computer, designed and optimized for 7 nanometers and beyond. Manufactured by contract manufacturer TSMC, the WSE-2 more than doubles all performance characteristics on the chip — the transistor count, core count, memory, memory bandwidth, and fabric bandwidth — over the first generation WSE. The result is that on every performance metric, the WSE-2 is orders of magnitude larger and more performant than any competing GPU on the market, Feldman said.

TSMC put the first WSE-1 chip in a museum of innovation for chip technology in Taiwan.

“Cerebras does deliver the cores promised,” Patrick Moorhead, an analyst at Moor Insights & Strategy. “What the company is delivering is more along the lines of multiple clusters on a chip. It does appear to give Nvidia a run for its money but doesn’t run raw CUDA. That has become somewhat of a de facto standard. Nvidia solutions are more flexible as well as they can fit into nearly any server chassis.”

With every component optimized for AI work, the CS-2 delivers more compute performance at less space and less power than any other system, Feldman said. Depending on workload, from AI to high-performance computing, CS-2 delivers hundreds or thousands of times more performance than legacy alternatives, and it does so at a fraction of the power draw and space.

A single CS-2 replaces clusters of hundreds or thousands of graphics processing units (GPUs) that consume dozens of racks, use hundreds of kilowatts of power, and take months to configure and program. At only 26 inches tall, the CS-2 fits in one-third of a standard datacenter rack.

“Obviously, there are companies and entities interested in Cerebras’ wafer-scale solution for large data sets,” said Jim McGregor, principal analyst at Tirias Research, in an email. “But, there are many more opportunities at the enterprise level for the millions of other AI applications and still opportunities beyond what Cerebras could handle, which is why Nvidia has the SuprPod and Selene supercomputers.”

He added, “You also have to remember that Nvidia is targeting everything from AI robotics with Jenson to supercomputers. Cerebras is more of a niche platform. It will take some opportunities but will not match the breadth of what Nvidia is targeting. Besides, Nvidia is selling everything they can build.”

Lots of customers

Above: Comparing the new Cerebras chip to its rival, the Nvidia A100.

Image Credit: Cerebras

And the company has proven itself by shipping the first generation to customers. Over the past year, customers have deployed the Cerebras WSE and CS-1, including Argonne National Laboratory; Lawrence Livermore National Laboratory; Pittsburgh Supercomputing Center (PSC) for its Neocortex AI supercomputer; EPCC, the supercomputing center at the University of Edinburgh; pharmaceutical leader GlaxoSmithKline; Tokyo Electron Devices; and more. Customers praising the chip include those at GlaxoSmithKline and the Argonne National Laboratory.

Kim Branson, senior vice president at GlaxoSmithKline, said in a statement that the company has increased the complexity of the encoder models it generates while decreasing training time by 80 times. At Argonne, the chip is being used for cancer research and has reduced the experiment turnaround time on cancer models by more than 300 times.

“For drug discovery, we have other wins that we’ll be announcing over the next year in heavy manufacturing and pharma and biotech and military,” Feldman said.

The new chips will ship in the third quarter. Feldman said the company now has more than 300 engineers, with offices in Silicon Valley, Toronto, San Diego, and Tokyo.

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[FJB] A new era of innovation: Moore’s Law is not dead and AI is ready to explode - ...

FJB — 4/11/2021 5:14:26 PM

A new era of innovation: Moore’s Law is not dead and AI is ready to explode

- SiliconANGLE

Dave Vellante with David Floyer

siliconangle.com /2021/04/10/new-era-innovation-moores-law-not-dead-ai-ready-explode/
4/10/2021
Moore’s Law is dead, right? Think again.

Although the historical annual improvement of about 40% in central processing unit performance is slowing, the combination of CPUs packaged with alternative processors is improving at a rate of more than 100% per annum. These unprecedented and massive improvements in processing power combined with data and artificial intelligence will completely change the way we think about designing hardware, writing software and applying technology to businesses.

Every industry will be disrupted. You hear that all the time. Well, it’s absolutely true and we’re going to explain why and what it all means.

In this Breaking Analysis, we’re going to unveil some data that suggests we’re entering a new era of innovation where inexpensive processing capabilities will power an explosion of machine intelligence applications. We’ll also tell you what new bottlenecks will emerge and what this means for system architectures and industry transformations in the coming decade.

Is Moore’s Law really dead?

We’ve heard it hundreds of times in the past decade. EE Times has written about it, MIT Technology Review, CNET, SiliconANGLE and even industry associations that marched to the cadence of Moore’s Law. But our friend and colleague Patrick Moorhead got it right when he said:

Moore’s Law, by the strictest definition of doubling chip densities every two years, isn’t happening anymore.

And that’s true. He’s absolutely correct. However, he couched that statement saying “by the strictest definition” for a reason… because he’s smart enough to know that the chip industry are masters at figuring out workarounds.

Historical performance curves are being shatteredThe graphic below is proof that the death of Moore’s Law by its strictest definition is irrelevant.

The fact is that the historical outcome of Moore’s Law is actually accelerating, quite dramatically. This graphic digs into the progression of Apple Inc.’s system-on-chip developments from the A9 and culminating in the A14 five-nanometer Bionic system on a chip.

The vertical axis shows operations per second and and the horizontal axis shows time for three processor types. The CPU, measured in terahertz (the blue line which you can hardly see); the graphics processing unit or GPU, measured in trillions of floating point operations per second (orange); and the neural processing unit or NPU, measured in trillions of operations per second (the exploding gray area).

Many folks will remember that historically, we rushed out to buy the latest and greatest personal computer because the newer models had faster cycle times, that is, more gigahertz. The outcome of Moore’s Law was that performance would double every 24 months or about 40% annually. CPU performance improvements have now slowed to roughly 30% annually, so technically speaking, Moore’s Law is dead.

Apple’s SoC performance shatters the normCombined, the improvements in Apple’s SoC since 2015 have been on a pace that’s higher than 118% annual improvement. Actually it’s higher because 118% is the actual figure for these three processor types shown above. In the graphic, we’re not even counting the impact of the digital signal processors and accelerator components of the system, which would push this higher.

Apple’s A14 shown above on the right is quite amazing with its 64-bit architecture, multiple cores and alternative processor types. But the important thing is what you can do with all this processing power – in an iPhone! The types of AI continue to evolve from facial recognition to speech and natural language processing, rendering videos, helping the hearing impaired and eventually bringing augmented reality to the palm of your hand.

Quite incredible.

Processing goes to the edge – networks and storage become the bottlenecksWe recently reported Microsoft Corp. Chief Executive Satya Nadella’s epic quote that we’ve reached peak centralization. The graphic below paints a picture that is telling. We just shared above that processing power is accelerating at unprecedented rates. And costs are dropping like a rock. Apple’s A14 costs the company $50 per chip. Arm at its v9 announcement said that it will have chips that can go into refrigerators that will optimize energy use and save 10% annually on power consumption. They said that chip will cost $1 — a buck to shave 10% off your electricity bill from the fridge.

Processing is plentiful and cheap. But look at where the expensive bottlenecks are: networks and storage. So what does this mean?

It means that processing is going to get pushed to the edge – wherever the data is born. Storage and networking will become increasingly distributed and decentralized. With custom silicon and processing power placed throughout the system with AI embedded to optimize workloads for latency, performance, bandwidth, security and other dimensions of value.

And remember, most of the data – 99% – will stay at the edge. We like to use Tesla Inc. as an example. The vast majority of data a Tesla car creates will never go back to the cloud. It doesn’t even get persisted. Tesla saves perhaps five minutes of data. But some data will connect occasionally back to the cloud to train AI models – we’ll come back to that.

But this picture above says if you’re a hardware company, you’d better start thinking about how to take advantage of that blue line, the explosion of processing power. Dell Technologies Inc., Hewlett Packard Enterprise Co., Pure Storage Inc., NetApp Inc. and the like are either going to start designing custom silicon or they’re going to be disrupted, in our view. Amazon Web Services Inc., Google LLC and Microsoft are all doing it for a reason, as are Cisco Systems Inc. and IBM Corp.. As cloud consultant Sarbjeet Johal has said, “this is not your grandfather’s semiconductor business.”

And if you’re a software engineer, you’re going to be writing applications that take advantage of of all the data being collected and bringing to bear this immense processing power to create new capabilities like we’ve never seen before.

AI everywhereMassive increases in processing power and cheap silicon will power the next wave of AI, machine intelligence, machine learning and deep learning.

We sometimes use artificial intelligence and machine intelligence interchangeably. This notion comes from our collaborations with author David Moschella. Interestingly, in his book “ Seeing Digital,” Moschella says “there’s nothing artificial” about this:

There’s nothing artificial about machine intelligence just like there’s nothing artificial about the strength of a tractor.

It’s a nuance, but precise language can often bring clarity. We hear a lot about machine learning and deep learning and think of them as subsets of AI. Machine learning applies algorithms and code to data to get “smarter” – make better models, for example, that can lead to augmented intelligence and better decisions by humans, or machines. These models improve as they get more data and iterate over time.

Deep learning is a more advanced type of machine learning that uses more complex math.

The right side of the chart above shows the two broad elements of AI. The point we want to make here is that much of the activity in AI today is focused on building and training models. And this is mostly happening in the cloud. But we think AI inference will bring the most exciting innovations in the coming years.

AI inference unlocks huge valueInference is the deployment of the model, taking real-time data from sensors, processing data locally, applying the training that has been developed in the cloud and making micro-adjustments in real time.

Let’s take an example. We love car examples and observing Tesla is instructive and a good model as to how the edge may evolve. So think about an algorithm that optimizes the performance and safety of a car on a turn. The model takes inputs with data on friction, road conditions, angles of the tires, tire wear, tire pressure and the like. And the model builders keep testing and adding data and iterating the model until it’s ready to be deployed.

Then the intelligence from this model goes into an inference engine, which is a chip running software, that goes into a car and gets data from sensors and makes micro adjustments in real time on steering and braking and the like. Now as we said before, Tesla persists the data for a very short period of time because there’s so much data. But it can choose to store certain data selectively if needed to send back to the cloud and further train the model. For example, if an animal runs into the road during slick conditions, maybe Tesla persists that data snapshot, sends it back to the cloud, combines it with other data and further perfects the model to improve safety.

This is just one example of thousands of AI inference use cases that will further develop in the coming decade.

AI value shifts from modeling to inferencingThis conceptual chart below shows percent of spend over time on modeling versus inference. And you can see some of the applications that get attention today and how these apps will mature over time as inference becomes more mainstream. The opportunities for AI inference at the edge and in the “internet of things” are enormous.

Modeling will continue to be important. Today’s prevalent modeling workloads in fraud, adtech, weather, pricing, recommendation engines and more will just keep getting better and better. But inference, we think, is where the rubber meets the road, as shown in the previous example.

And in the middle of the graphic we show the industries, which will all be transformed by these trends.

One other point on that: Moschella in his book explains why historically, vertical industries remained pretty stovepiped from each other. They each had their own “stack” of production, supply, logistics, sales, marketing, service, fulfillment and the like. And expertise tended to reside and stay within that industry and companies, for the most part, stuck to their respective swim lanes.

But today we see so many examples of tech giants entering other industries. Amazon entering grocery, media and healthcare, Apple in finance and EV, Tesla eyeing insurance: There are many examples of tech giants crossing traditional industry boundaries and the enabler is data. Auto manufacturers over time will have better data than insurance companies for example. DeFi or decentralized finance or platforms using the blockchain will continue to improve with AI and disrupt traditional payment systems — and on and on.

Hence we believe the oft-repeated bromide that no industry is safe from disruption.

Snapshot of AI in the enterpriseLast week we showed you the chart below from Enterprise Technology Research.

This is data shows on the vertical axis Net Score or spending momentum. The horizontal axis is Market Share or pervasiveness in the ETR data set. The red line at 40% is our subjective anchor; anything about 40% is really good in our view.

Machine learning and AI are the No. 1 area of spending velocity and has been for a while, hence the four stars. Robotic process automation is increasingly an adjacency to AI and you could argue cloud is where all the machine learning action is taking place today and is another adjacency, although we think AI continues to move out of the cloud for the reasons we just described.

Enterprise AI specialists carve out positionsThe chart below shows some of the vendors in the space that are gaining traction. These are the companies chief information officers and information technology buyers associate with their AI/ML spend.

This graph above uses the same Y/X coordinates – Spending Velocity on the vertical by Market Share on the horizontal axis, same 40% red line.

The big cloud players, Microsoft, AWS and Google, dominate AI and ML with the most presence. They have the tooling and the data. As we said, lots of modeling is going on in the cloud, but this will be pushed into remote AI inference engines that will have massive processing capabilities collectively. We are moving away from peak centralization and this presents great opportunities to create value and apply AI to industry.

Databricks Inc. is seen as an AI leader and stands out with a strong Net Score and a prominent Market Share. SparkCognition Inc. is off the charts in the upper left with an extremely high Net Score albeit from a small sample. The company applies machine learning to massive data sets. DataRobot Inc. does automated AI – they’re super high on the Y axis. Dataiku Inc. helps create machine learning-based apps. C3.ai Inc. is an enterprise AI company founded and run by Tom Siebel. You see SAP SE, Salesforce.com Inc. and IBM Watson just at the 40% line. Oracle is also in the mix with its autonomous database capabilities and Adobe Inc. shows as well.

The point is that these software companies are all embedding AI into their offerings. And incumbent companies that are trying not to get disrupted can buy AI from software companies. They don’t have to build it themselves. The hard part is how and where to apply AI. And the simple answer is: Follow the data.

Key takeawaysThere’s so much more to this story, but let’s leave it there for now and summarize.

We’ve been pounding the table about the post-x86 era, the importance of volume in terms of lowering the costs of semiconductor production, and today we’ve quantified something that we haven’t really seen much of and that’s the actual performance improvements we’re seeing in processing today. Forget Moore’s Law being dead – that’s irrelevant. The original premise is being blown away this decade by SoC and the coming system on package designs. Who knows with quantum computing what the future holds in terms of performance increases.

These trends are a fundamental enabler of AI applications and as is most often the case, the innovation is coming from consumer use cases; Apple continues to lead the way. Apple’s integrated hardware and software approach will increasingly move to the enterprise mindset. Clearly the cloud vendors are moving in that direction. You see it with Oracle Corp. too. It just makes sense that optimizing hardware and software together will gain momentum because there’s so much opportunity for customization in chips as we discussed last week with Arm Ltd.’s announcement – and it’s the direction new CEO Pat Gelsinger is taking Intel Corp.

One aside – Gelsinger may face massive challenges with Intel, but he’s right on that semiconductor demand is increasing and there’s no end in sight.

If you’re an enterprise, you should not stress about inventing AI. Rather, your focus should be on understanding what data gives you competitive advantage and how to apply machine intelligence and AI to win. You’ll buy, not build AI.

Data, as John Furrier has said many times, is becoming the new development kit. He said that 10 years ago and it’s more true now than ever before:

Data is the new development kit.

If you’re an enterprise hardware player, you will be designing your own chips and writing more software to exploit AI. You’ll be embedding custom silicon and AI throughout your product portfolio and you’ll be increasingly bringing compute to data. Data will mostly stay where it’s created. Systems, storage and networking stacks are all being disrupted.

If you developer software, you now have processing capabilities in the palm of your hands that are incredible and you’re going to write new applications to take advantage of this and use AI to change the world. You’ll have to figure out how to get access to the most relevant data, secure your platforms and innovate.

And finally, if you’re a services company you have opportunities to help companies trying not to be disrupted. These are many. You have the deep industry expertise and horizontal technology chops to help customers survive and thrive.

Privacy? AI for good? Those are whole topics on their own, extensively covered by journalists. We think for now it’s prudent to gain a better understanding of how far AI can go before we determine how far it should go and how it should be regulated. Protecting our personal data and privacy should be something that we most definitely care for – but generally we’d rather not stifle innovation at this point.

Keep in touchRemember these episodes are all available as podcasts wherever you listen. Email david.vellante@siliconangle.com, DM @dvellante on Twitter and comment on our LinkedIn posts.

Also, check out this ETR Tutorial we created, which explains the spending methodology in more detail. Note: ETR is a separate company from Wikibon/SiliconANGLE. If you would like to cite or republish any of the company’s data, or inquire about its services, please contact ETR at legal@etr.ai.

Here’s the full video analysis:

[FJB] ‘Last Hope’ Experiment Finds Evidence for Unknown Particles By Natalie Wolchover...

FJB — 4/8/2021 3:24:12 PM

‘Last Hope’ Experiment Finds Evidence for Unknown Particles
By Natalie Wolchover
April 7, 2021

quantamagazine.org

Twenty years after an apparent anomaly in the behavior of elementary particles raised hopes of a major physics breakthrough, a new measurement has solidified them: Physicists at Fermi National Accelerator Laboratory near Chicago announced today that muons — elementary particles similar to electrons — wobbled more than expected while whipping around a magnetized ring.

The widely anticipated new measurement confirms the decades-old result, which made headlines around the world. Both measurements of the muon’s wobbliness, or magnetic moment, significantly overshoot the theoretical prediction, as calculated last year by an international consortium of 132 theoretical physicists. The Fermilab researchers estimate that the difference has grown to a level quantified as “4.2 sigma,” well on the way to the stringent five-sigma level that physicists need to claim a discovery.

Taken at face value, the discrepancy strongly suggests that unknown particles of nature are giving muons an extra push. Such a discovery would at long last herald the breakdown of the 50-year-old Standard Model of particle physics — the set of equations describing the known elementary particles and interactions.

“Today is an extraordinary day, long awaited not only by us but by the whole international physics community,” Graziano Venanzoni, one of the leaders of the Fermilab Muon g-2 experiment and a physicist at the Italian National Institute for Nuclear Physics, told the press.

However, even as many particle physicists are likely to be celebrating — and racing to propose new ideas that could explain the discrepancy — a paper published today in the journal Nature casts the new muon measurement in a dramatically duller light.

The paper, which appeared just as the Fermilab team unveiled its new measurement, suggests that the muon’s measured wobbliness is exactly what the Standard Model predicts.

In the paper, a team of theorists known as BMW present a state-of-the-art supercomputer calculation of the most uncertain term that goes into the Standard Model prediction of the muon’s magnetic moment. BMW calculates this term to be considerably larger than the value adopted last year by the consortium, a group known as the Theory Initiative. BMW’s larger term leads to a larger overall predicted value of the muon’s magnetic moment, bringing the prediction in line with the measurements.

If the new calculation is correct, then physicists may have spent 20 years chasing a ghost. But the Theory Initiative’s prediction relied on a different calculational approach that has been honed over decades, and it could well be right. In that case, Fermilab’s new measurement constitutes the most exciting result in particle physics in years.

“This is a very sensitive and interesting situation,” said Zoltan Fodor, a theoretical particle physicist at Pennsylvania State University who is part of the BMW team.

BMW’s calculation itself is not breaking news; the paper first appeared as a preprint last year. Aida El-Khadra, a particle theorist at the University of Illinois who co-organized the Theory Initiative, explained that the BMW calculation should be taken seriously, but that it wasn’t factored into the Theory Initiative’s overall prediction because it still needed vetting. If other groups independently verify BMW’s calculation, the Theory Initiative will integrate it into its next assessment.

Dominik Stöckinger, a theorist at the Technical University of Dresden who participated in the Theory Initiative and is a member of the Fermilab Muon g-2 team, said the BMW result creates “an unclear status.” Physicists can’t say whether exotic new particles are pushing on muons until they agree about the effects of the 17 Standard Model particles they already know about.

Regardless, there’s plenty of reason for optimism: Researchers emphasize that even if BMW is right, the puzzling gulf between the two calculations could itself point to new physics. But for the moment, the past 20 years of conflict between theory and experiment appear to have been replaced by something even more unexpected: a battle of theory versus theory.

Momentous MuonsThe reason physicists have eagerly awaited Fermilab’s new measurement is that the muon’s magnetic moment — essentially the strength of its intrinsic magnetism — encodes a huge amount of information about the universe.

A century ago, physicists assumed that the magnetic moments of elementary particles would follow the same formula as larger objects. Instead they found that electrons rotate in magnetic fields twice as much as expected. Their “gyromagnetic ratio,” or “g-factor” — the number relating their magnetic moment to their other properties — seemed to be 2, not 1, a surprise discovery later explained by the fact that electrons are “spin-1/2” particles, which return to the same state after making two full turns rather than one.

For years, both electrons and muons were thought to have g-factors of exactly 2. But then in 1947, Polykarp Kusch and Henry Foley measured the electron’s g-factor to be 2.00232. The theoretical physicist Julian Schwinger almost immediately explained the extra bits: He showed that the small corrections come from an electron’s tendency to momentarily emit and reabsorb a photon as it moves through space.

Many other fleeting quantum fluctuations happen as well. An electron or muon might emit and reabsorb two photons, or a photon that briefly becomes an electron and a positron, among countless other possibilities that the Standard Model allows. These temporary manifestations travel around with an electron or muon like an entourage, and all of them contribute to its magnetic properties. “The particle you thought was a bare muon is actually a muon plus a cloud of other things that appear spontaneously,” said Chris Polly, another leader of the Fermilab Muon g-2 experiment. “They change the magnetic moment.”

The rarer a quantum fluctuation, the less it contributes to the electron or muon’s g-factor. “As you go further into the decimal places you can see where suddenly the quarks start to appear for the first time,” said Polly. Further along are particles called W and Z bosons, and so on. Because muons are 207 times heavier than electrons, they’re about 2072 (or 43,000) times more likely to conjure up heavy particles in their entourage; these particles therefore alter the muon’s g-factor far more than an electron’s. “So if you’re looking for particles that could explain the missing mass of the universe — dark matter — or you’re looking for particles of a theory called supersymmetry,” Polly said, “that’s where the muon has a unique role.”

For decades, theorists have strived to calculate contributions to the muon’s g-factor coming from increasingly unlikely iterations of known particles from the Standard Model, while experimentalists measured the g-factor with ever-increasing precision. If the measurement were to outstrip the expectation, this would betray the presence of strangers in the muon’s entourage: fleeting appearances of particles beyond the Standard Model.

Muon magnetic moment measurements began at Columbia University in the 1950s and were picked up a decade later at CERN, Europe’s particle physics laboratory. There, researchers pioneered the measurement technique still used at Fermilab today.

High-speed muons are shot into a magnetized ring. As a muon whips around the ring, passing through its powerful magnetic field, the particle’s spin axis (which can be pictured as a little arrow) gradually rotates. Millionths of a second later, typically after speeding around the ring a few hundred times, the muon decays, producing an electron that flies into one of the surrounding detectors. The varying energies of electrons emanating from the ring at different times reveal how quickly the muon spins are rotating.

In the 1990s, a team at Brookhaven National Laboratory on Long Island built a 50-foot-wide ring to fling muons around and began collecting data. In 2001, the researchers announced their first results, reporting 2.0023318404 for the muon’s g-factor, with some uncertainty in the final two digits. Meanwhile, the most comprehensive Standard Model prediction at the time gave the significantly lower value of 2.0023318319.

It instantly became the world’s most famous eighth-decimal-place discrepancy.

“Hundreds of newspapers covered it,” said Polly, who was a graduate student with the experiment at the time.

Brookhaven’s measurement overshot the prediction by nearly three times its supposed margin of error, known as a three-sigma deviation. A three-sigma gap is significant, unlikely to be caused by random noise or an unlucky accumulation of small errors. It strongly suggested that something was missing from the theoretical calculation, something like a dark matter particle or an extra force-carrying boson.

But unlikely sequences of events sometimes happen, so physicists require a five-sigma deviation between a prediction and a measurement to definitively claim a discovery.

Trouble With HadronsA year after Brookhaven’s headline-making measurement, theorists spotted a mistake in the prediction. A formula representing one group of the tens of thousands of quantum fluctuations that muons can engage in contained a rogue minus sign; fixing it in the calculation reduced the difference between theory and experiment to just two sigma. That’s nothing to get excited about.

But as the Brookhaven team accrued 10 times more data, their measurement of the muon’s g-factor stayed the same while the error bars around the measurement shrank. The discrepancy with theory grew back to three sigma by the time of the experiment’s final report in 2006. And it continued to grow, as theorists kept honing the Standard Model prediction for the g-factor without seeing the value drift upward toward the measurement.

The Brookhaven anomaly loomed ever larger in physicists’ psyches as other searches for new particles failed. Throughout the 2010s, the $20 billion Large Hadron Collider in Europe slammed protons together in hopes of conjuring up dozens of new particles that might complete the pattern of nature’s building blocks. But the collider found only the Higgs boson — the last missing piece of the Standard Model. Meanwhile, a slew of experimental searches for dark matter found nothing. Hopes for new physics increasingly rode on wobbly muons. “I don’t know if it is the last great hope for new physics, but it certainly is a major one,” Matthew Buckley, a particle physicist at Rutgers University, told me.

The original Muon g-2 experiment was constructed at Brookhaven National Laboratory on Long Island in the 1990s. Rather than build a new experiment from scratch, physicists used a series of barges and trucks to move the 700-ton electromagnetic ring down the Atlantic coast, across the Gulf of Mexico, and up the Mississippi, Illinois and Des Plaines rivers to the Fermi National Laboratory in Illinois. Thousands of people came out to celebrate its arrival in July 2013.

Darin Clifton/Ceres Barge; Reidar Hahn

Everyone knew that in order to cross the threshold of discovery, they would need to measure the muon’s gyromagnetic ratio again, and more precisely. So plans for a follow-up experiment got underway. In 2013, the giant magnet used at Brookhaven was loaded onto a barge off Long Island and shipped down the Atlantic Coast and up the Mississippi and Illinois rivers to Fermilab, where the lab’s powerful muon beam would let data accrue much faster than before. That and other improvements would allow the Fermilab team to measure the muon’s g-factor four times more accurately than Brookhaven had.

In 2016, El-Khadra and others started organizing the Theory Initiative, seeking to iron out any disagreements and arrive at a consensus Standard Model prediction of the g-factor before the Fermilab data rolled in. “For the impact of such an exquisite experimental measurement to be maximized, theory needs to get its act together, basically,” she said, explaining the reasoning at the time. The theorists compared and combined calculations of different quantum bits and pieces that contribute to the muon’s g-factor and arrived at an overall prediction last summer of 2.0023318362. That fell a hearty 3.7 sigma below Brookhaven’s final measurement of 2.0023318416.

But the Theory Initiative’s report was not the final word.

Uncertainty about what the Standard Model predicts for the muon’s magnetic moment stems entirely from the presence in its entourage of “hadrons”: particles made of quarks. Quarks feel the strong force (one of the three forces of the Standard Model), which is so strong it’s as if quarks are swimming in glue, and that glue is endlessly dense with other particles. The equation describing the strong force (and thus, ultimately, the behavior of hadrons) can’t be exactly solved.

That makes it hard to gauge how often hadrons pop up in the muon’s midst. The dominant scenario is the following: The muon, as it travels along, momentarily emits a photon, which morphs into a hadron and an antihadron; the hadron-antihadron pair quickly annihilate back into a photon, which the muon then reabsorbs. This process, called hadronic vacuum polarization, contributes a small correction to the muon’s gyromagnetic ratio starting in the seventh decimal place. Calculating this correction involves solving a complicated mathematical sum for each hadron-antihadron pair that can arise.

Uncertainty about this hadronic vacuum polarization term is the primary source of overall uncertainty about the g-factor. A small increase in this term can completely erase the difference between theory and experiment. Physicists have two ways to calculate it.

With the first method, researchers don’t even try to calculate the hadrons’ behavior. Instead, they simply translate data from other particle collision experiments into an expectation for the hadronic vacuum polarization term. “The data-driven approach has been refined and optimized over decades, and several competing groups using different details in their approaches have confirmed each other,” said Stöckinger. The Theory Initiative used this data-driven approach.

But in recent years, a purely computational method has been steadily improving. In this approach, researchers use supercomputers to solve the equations of the strong force at discrete points on a lattice instead of everywhere in space, turning the infinitely detailed problem into a finite one. This way of coarse-graining the quark quagmire to predict the behavior of hadrons “is similar to a weather forecast or meteorology,” Fodor explained. The calculation can be made ultra-precise by putting lattice points very close together, but this also pushes computers to their limits.

The 14-person BMW team — named after Budapest, Marseille and Wuppertal, the three European cities where most team members were originally based — used this approach. They made four chief innovations. First they reduced random noise. They also devised a way of very precisely determining scale in their lattice. At the same time, they more than doubled their lattice’s size compared to earlier efforts, so that they could study hadrons’ behavior near the center of the lattice without worrying about edge effects. Finally, they included in the calculation a family of complicating details that are often neglected, like mass differences between types of quarks. “All four [changes] needed a lot of computing power,” said Fodor.

The researchers then commandeered supercomputers in Jülich, Munich, Stuttgart, Orsay, Rome, Wuppertal and Budapest and put them to work on a new and better calculation. After several hundred million core hours of crunching, the supercomputers spat out a value for the hadronic vacuum polarization term. Their total, when combined with all other quantum contributions to the muon’s g-factor, yielded 2.00233183908. This is “in fairly good agreement” with the Brookhaven experiment, Fodor said. “We cross-checked it a million times because we were very much surprised.” In February 2020, they posted their work on the arxiv.org preprint server.

The Theory Initiative decided not to include BMW’s value in their official estimate for a few reasons. The data-driven approach has a slightly smaller error bar, and three different research groups independently calculated the same thing. In contrast, BMW’s lattice calculation was unpublished as of last summer. And although the result agrees well with earlier, less precise lattice calculations that also came out high, it hasn’t been independently replicated by another group to the same precision.

The Theory Initiative’s decision meant that the official theoretical value of the muon’s magnetic moment had a 3.7-sigma difference with Brookhaven’s experimental measurement. It set the stage for what has become the most anticipated reveal in particle physics since the Higgs boson in 2012.

The RevelationsA month ago, the Fermilab Muon g-2 team announced that they would present their first results today. Particle physicists were ecstatic. Laura Baudis, a physicist at the University of Zurich, said she was “counting the days until April 7,” after anticipating the result for 20 years. “If the Brookhaven results are confirmed by the new experiment at Fermilab,” she said, “this would be an enormous achievement.”

And if not — if the anomaly were to disappear — some in the particle physics community feared nothing less than “the end of particle physics,” said Stöckinger. The Fermilab g-2 experiment is “our last hope of an experiment which really proves the existence of physics beyond the Standard Model,” he said. If it failed to do so, many researchers might feel that “we now give up and we have to do something else instead of researching physics beyond the Standard Model.” He added, “Honestly speaking, it might be my own reaction.”

The 200-person Fermilab team revealed the result to themselves only six weeks ago in an unveiling ceremony over Zoom. Tammy Walton, a scientist on the team, rushed home to catch the show after working the night shift on the experiment, which is currently in its fourth run. (The new analysis covers data from the first run, which makes up 6% of what the experiment will eventually accrue.) When the all-important number appeared on the screen, plotted along with the Theory Initiative’s prediction and the Brookhaven measurement, Walton was thrilled to see it land higher than the former and pretty much smack dab on top of the latter. “People are going to be crazy excited,” she said.

Papers proposing various ideas for new physics are expected to flood the arxiv in the coming days. Yet beyond that, the future is unclear. What was once an illuminating breach between theory and experiment has been clouded by a far foggier clash of calculations.

It’s possible that the supercomputer calculation will turn out to be wrong — that BMW overlooked some source of error. “We need to have a close look at the calculation,” El-Khadra said, stressing that it’s too early to draw firm conclusions. “It is pushing on the methods to get that precision, and we need to understand if the way they pushed on the methods broke them.”

That would be good news for fans of new physics.

Interestingly, though, even if the data-driven method is the approach with an unidentified problem under the hood, theorists have a hard time understanding what the problem could be other than unaccounted-for new physics. “The need for new physics would only shift elsewhere,” said Martin Hoferichter of the University of Bern, a leading member of the Theory Initiative.

Researchers who have been exploring possible problems with the data-driven method over the past year say the data itself is unlikely to be wrong. It comes from decades of ultraprecise measurements of 35 hadronic processes. But “it could be that the data, or the way it is interpreted, is misleading,” said Andreas Crivellin of CERN and other institutions, a coauthor (along with Hoferichter) of one paper studying this possibility.

It’s possible, he explained, that destructive interference happens to reduce the likelihood of the hadronic processes arising in certain electron-positron collisions, without affecting hadronic vacuum polarization near muons; then the data-driven extrapolation from one to the other doesn’t quite work. In that case, though, another Standard Model calculation that’s sensitive to the same hadronic processes gets thrown off, creating a different tension between the theory and data. And this tension would itself suggest new physics.

It’s tricky to resolve this other tension while keeping the new physics “elusive enough to not have been observed elsewhere,” as El-Khadra put it, yet it’s possible — for instance, by introducing the effects of hypothetical particles called vector-like leptons.

Thus the mystery swirling around muons might lead the way past the Standard Model to a more complete account of the universe after all. However things turn out, it’s safe to say that today’s news — both the result from Fermilab, as well as the publication of the BMW calculation in Nature — is not the end for particle physics.

[FJB] The Unparalleled Genius of John von Neumann - Cantor’s Paradise ...

FJB — 4/7/2021 11:30:13 AM

The Unparalleled Genius of John von Neumann

- Cantor’s Paradise
Jørgen Veisdal
cantorsparadise.com

The von Neumann Essays

This story is also available on Kindle!

“Most mathematicians prove what they can, von Neumann proves what he wants”

It is indeed supremely difficult to effectively refute the claim that John von Neumann is likely the most intelligent person who has ever lived. By the time of his death in 1957 at the modest age of 53, the Hungarian polymath had not only revolutionized several subfields of mathematics and physics but also made foundational contributions to pure economics and statistics and taken key parts in the invention of the atomic bomb, nuclear energy and digital computing.

Known now as “the last representative of the great mathematicians”, von Neumann’s genius was legendary even in his own lifetime. The sheer breadth of stories and anecdotes about his brilliance, from Nobel Prize-winning physicists to world-class mathematicians abound:

”You know, Herb, Johnny can do calculations in his head ten times as fast as I can. And I can do them ten times as fast as you can, so you can see how impressive Johnny is” — Enrico Fermi (Nobel Prize in Physics, 1938)

“One had the impression of a perfect instrument whose gears were machined to mesh accurately to a thousandth of an inch.” — Eugene Wigner (Nobel Prize in Physics, 1963)

“I have sometimes wondered whether a brain like von Neumann’s does not indicate a species superior to that of man” — Hans Bethe (Nobel Prize in Physics, 1967)

And indeed, von Neumann both worked alongside and collaborated with some of the foremost figures of twentieth century science. He went to high school with Eugene Wigner, collaborated with Hermann Weyl at ETH, attended lectures by Albert Einstein in Berlin, worked under David Hilbert at Göttingen, with Alan Turing and Oskar Morgenstern in Princeton, with Niels Bohr in Copenhagen and was close with both Richard Feynman and J. Robert Oppenheimer at Los Alamos.

An émigré to America in 1933, von Neumann’s life was one famously dedicated to cognitive and creative pursuits, but also the enjoyments of life. Twice married and wealthy, he loved expensive clothes, hard liquor, fast cars and dirty jokes, according to his friend Stanislaw Ulam. Almost involuntarily, his posthumous biographer Norman Macrae recounts, people took a liking to von Neumann, even those who disagreed with his conservative politics (Regis, 1992).

This essay aims to highlight some of the unbelievable feats of “Johnny” von Neumann’s mind. Happy reading!

Early years (1903–1921)Neumann János Lajos (John Louis Neumann in English) was born (or “ arrived”) on December 28th 1903 in Budapest, Hungary. Born to wealthy non-observant Jewish bankers, his upbringing can be described as privileged. His father held a doctorate in law, and he grew up in an 18-room apartment on the top floor above the Kann-Heller offices at 62 Bajcsy-Zsilinszky Street in Budapest (Macrae, 1992).

John von Neumann at age 7 (1910)Child prodigy“Johnny” von Neumann was a child prodigy. Even from a young age, there were strange stories of little John Louis’ abilities: dividing two eight-digit numbers in his head and conversing in Ancient Greek at age six (Henderson, 2007), proficient in calculus at age eight (Nasar, 1998) and reading Emile Borel’s Théorie des Fonctions (“On some points in the theory of functions” ) at age twelve (Leonard, 2010). Reportedly, von Neumann possessed an eidetic memory, and so was able to recall complete novels and pages of the phone directory on command. This enabled him to accumulate an almost encyclopedic knowledge of what ever he read, such as the history of the Peloponnesian Wars, the Trial Joan of Arc and Byzantine history (Leonard, 2010). A Princeton professor of the latter topic once stated that by the time he was in his thirties, Johnny had greater expertise in Byzantine history than he did (Blair, 1957).

Left: John von Neumann at age 11 (1915) with his cousin Katalin Alcsuti. (Photo: Nicholas Vonneumann). Right: The Neumann brothers Miklós (1911–2011), Mihály (1907–1989) and János Lajos (1903–1957)

"One of his remarkable abilities was his power of absolute recall. As far as I could tell, von Neumann was able on once reading a book or article to quote it back verbatim; moreover, he could do it years later without hesitation. He could also translate it at no diminution in speed from its original language into English. On one occasion I tested his ability by asking him to tell me how A Tale of Two Cities started. Whereupon, without any pause, he immediately began to recite the first chapter and continued until asked to stop after about ten or fifteen minutes."Excerpt, The Computer from Pascal to von Neumann by Herman Goldstein (1980)

An unconventional parent, von Neumann’s father Max would reportedly bring his workaday banking decisions home to the family and ask his children how they would have reacted to particular investment possibilities and balance-sheet risks (Macrae, 1992). He was home-schooled until 1914, as was the custom in Hungary at the time. Starting at the age of 11, he was enrolled in the German-speaking Lutheran Gymnasium in Budapest. He would attend the high school until 1921, famously overlapping the high school years of three other “ Martians” of Hungary:

Leo Szilard

nuclear chain reaction

Einstein-Szilard letter

Although all of similar ages and interests, as Macrae (1992) writes:

"The four Budapesters were as different as four men from similar backgrounds could be. They resembled one another only in the power of the intellects and in the nature of their professional careers. Wigner [...] is shy, painfully modest, quiet. Teller, after a lifetime of successful controversy, is emotional, extroverted and not one to hide his candle. Szilard was passionate, oblique, engagé, and infuriating. Johnny [...] was none of these. Johnny's most usual motivation was to try to make the next minute the most productive one for whatever intellectual business he had in mind."- Excerpt, John von Neumann by Norman Macrae (1992)

Yet still, the four would work together off and on as they all emigrated to America and got involved in the Manhattan Project.

By the time von Neumann enrolled in university in 1921, he had already written a paper with one of his tutors, Mikhail Fekete on “A generalization of Fejér’s theorem on the location of the roots of a certain kind of polynomial” (Ulam, 1958). Fekete had along with Laszló Rátz reportedly taken a notice to von Neumann and begun tutoring him in university-level mathematics. According to Ulam, even at the age of 18, von Neumann was already recognized as a full-fledged mathematician. Of an early set theory paper written by a 16 year old von Neumann, Abraham Fraenkel (of Zermelo-Fraenkel set theory fame) himself later stated (Ulam, 1958):

Letter from Abraham Fraenkel to Stanislaw Ulam
Around 1922-23, being then professor at Marburg University, I received from Professor Erhard Schmidt, Berlin [...] a long manuscript of an author unknown to me, Johann von Neumann, with the title Die Axiomatisierung der Mengerlehre, this being his eventual doctor dissertation which appeared in the Zeitschrift only in 1928 [...] I asked to express my view since it seemed incomprehensible. I don't maintain that I understood anything, but enough to see that this was an outstanding work, and to recognize ex ungue leonem [the claws of the lion]. While answering in this sense, I invited the young scholar to visit me in Marburg, and discussed things with him, strongly advising him to prepare the ground for the understanding of so technical an essay by a more informal essay which could stress the new access to the problem and its fundamental consequences. He wrote such an essay under the title Eine Axiomatisierung der Mengerlehre and I published it in 1925.

In University (1921–1926)As Macrae (1992) writes, there was never much doubt that Johnny would one day be attending university. Johnny’s father, Max, initially wanted him to follow in his footsteps and become a well-paid financier, worrying about the financial stability of a career in mathematics. However, with the help of the encouragement from Hungarian mathematicians such as Lipót Fejér and Rudolf Ortvay, his father eventually acquiesced and decided to let von Neumann pursue his passions, financing his studies abroad.

Johnny, apparently in agreement with his father, decided initially to pursue a career in chemical engineering. As he didn’t have any knowledge of chemistry, it was arranged that he could take a two-year non-degree course in chemistry at the University of Berlin. He did, from 1921 to 1923, afterwards sitting for and passing the entrance exam to the prestigious ETH Zurich. Still interested in pursuing mathematics, he also simultaneously entered University Pázmány Péter (now Eötvös Loránd University) in Budapest as a Ph.D. candidate in mathematics. His Ph.D. thesis, officially written under the supervision of Fejér, regarded the axiomatization of Cantor’s set theory. As he was officially in Berlin studying chemistry, he completed his Ph.D. largely in absentia, only appearing at the University in Budapest at the end of each term for exams. While in Berlin, he collaborated with Erhard Schmidt on set theory and also attended courses in physics, including statistical mechanics taught by Albert Einstein. At ETH, starting in 1923, he continued both his studies in chemistry and his research in mathematics.

“Evidently, a Ph.D. thesis and examinations did not constitute an appreciable effort” — Eugene Wigner

Two portraits of John von Neumann (1920s)In mathematics, he first studied Hilbert’s theory of consistency with German mathematician Hermann Weyl. He eventually graduated both as a chemical engineer from ETH and with Ph.D. in mathematics, summa cum laude from the University of Budapest in 1926 at 24 years old.

“There was a seminar for advanced students in Zürich that I was teaching and von Neumann was in the class. I came to a certain theorem, and I said it is not proved and it may be difficult. von Neumann didn’t say anything but after five minutes he raised his hand. When I called on him he went to the blackboard and proceeded to write down the proof. After that I was afraid of von Neumann” — George Pólya

From von Neumann’s Fellowship application to the International Education Board (1926)His application to the Rockefeller-financed International Education Board (above) for a six-month fellowship to continue his research at the University of Göttingen mentions Hungarian, German, English, French and Italian as spoken languages, and was accompanied by letters of recommendation from Richard Courant, Hermann Weyl and David Hilbert, three of the world’s foremost mathematicians at the time (Leonard, 2010).

In Göttingen (1926–1930)

The Auditorium Maximum at the University of Göttingen, 1935Johnny traveled to Göttingen in the fall of 1926 to continue his work in mathematics under David Hilbert, likely the world’s foremost mathematician of that time. Reportedly, according to Leonard (2010), von Neumann was initially attracted to Hilbert’s stance in the debate over so-called metamathematics, also known as formalism and that this is what drove him to study under Hilbert. In particular, in his fellowship application, he wrote of his wish to conduct (Leonard, 2010)

"Research over the bases of mathematics and of the general theory of sets, especially Hilbert's theory of uncontradictoriness [...], [investigations which] have the purpose of clearing up the nature of antinomies of the general theory of sets, and thereby to securely establish the classical foundations of mathematics. Such research render it possible to explain critically the doubts which have arisen in mathematics"

Very much both in the vein and language of Hilbert, von Neumann was likely referring to the fundamental questions posed by Georg Cantor regarding the nature of infinite sets starting in the 1880s. von Neumann, along with Wilhelm Ackermann and Paul Bernays would eventually become Hilbert’s key assistants in the elaboration of his Entscheidungsproblem (“decision problem”) initiated in 1918. By the time he arrived in Göttingen, von Neumann was already well acquainted with the topic, in addition to his Ph.D. dissertation having already published two related papers while at ETH.

Set theoryJohn von Neumann wrote a cluster of papers on set theory and logic while in his twenties:

von Neumann (1923).

Zur Einführung der transfiniten Zahlen

von Neumann (1925)

Eine Axiomatisierung der Mengenlehre

von Neumann-Bernays-Gödel set theory

von Neumann (1926)

Az általános halmazelmélet axiomatikus felépitése,

von Neumann (1928)

Die Axiomatisierung der Mengenlehre

Gödel and Berneys

von Neumann (1928)

“Über die Definition durch transfinite Induktion und verwandte Fragen der allgemeinen Mengenlehre”

paradoxes of set theory

axiom of choice

von Neumann (1929)

Über eine Widerspruchsfreiheitsfrage in der axiomatischen Mengenlehre

Summarized, von Neumann’s main contribution to set theory is what would become the von Neumann-Bernays-Gödel set theory (NBG), an axiomatic set theory that is considered a conservative extension of the accepted Zermelo-Fraenkel set theory (ZFC). It introduced the notion of class (a collection of sets defined by a formula whose quantifiers range only over sets) and can define classes that are larger than sets, such as the class of all sets and the class of all ordinal numbers.

Left: John von Neumann in the 1920s. Right: von Neumann, J (1923). Zur Einführung der transfiniten Zahlen (“On the introduction of transfinite numbers”). Acta Litterarum ac Scientiarum Regiae Universitatis Hungaricae Francisco-Josephinae, sectio scientiarum mathematicarum, 1, pp. 199–208.
Inspired by the works of Georg Cantor, Ernst Zermelo’s 1908 axioms for set theory and the 1922 critiques of Zermelo’s set theory by Fraenkel and Skolem, von Neumann’s work provided solutions to some of the problems of Zermelo set theory, leading to the eventual development of Zermelo-Fraenkel set theory (ZFC). The problems he helped resolve include:

Of course, following the critiques and further revisions of Zermelo’s set theory by Fraenkel, Skolem, Hilbert and von Neumann, a young mathematician by the name of Kurt Gödel in 1930 published a paper which would effectively end von Neumann’s efforts in formalist set theory, and indeed Hilbert’s formalist program altogether, his theorem of incompleteness. von Neumann happened to be in the audience when Gödel first presented it:

"At a mathematical conference preceding Hilbert's address, a quiet, obscure young man, Kurt Gödel, only a year beyond his PhD, announced a result which would forever change the foundations of mathematics. He formalized the liar paradox, "This statement is false" to prove roughly that for any effectively axiomatized consistent extension T of number theory (Peano arithmetic) there is a sentence s which asserts its own unprovability in T.John von Neumann, who was in the audience immediately understood the importance of Gödel's incompleteness theorem. He was at the conference representing Hilbert's proof theory program and recognized that Hilbert's program was over.In the next few weeks von Neumann realized that by arithmetizing the proof of Gödel's first theorem, one could prove an even better one, that no such formal system T could prove its own consistency. A few weeks later he brought his proof to Gödel, who thanked him and informed him politely that he had already submitted the second incompleteness theorem for publication."- Excerpt, Computability. Turing, Gödel, Church and Beyond by Copeland et al. (2015)

One of Gödel’s lifelong supporters, von Neumann later stated that

“Gödel is absolutely irreplaceable. In a class by himself.”

By the end of 1927, von Neumann had published twelve major papers in mathematics. His habilitation (qualification to conduct independent university teaching) was completed in December of 1927, and he began lecturing as a Privatdozent at the University of Berlin in 1928 at the age of 25, the youngest Privatdozent ever elected in the university’s history in any subject.

"By the middle of 1927 it was clearly desirable for the young eagle Johnny to soar from Hilbert's nest. Johnny had spent his undergraduate years explaining what Hilbert had got magnificently right but was now into his postgraduate years where had to explain what Hilbert had got wrong"- Excerpt, John von Neumann by Norman Macrae (1992)

Game theoryAround the same time he was making contributions to set theory, von Neumann also proved a theorem known as the minimax theorem for zero-sum games, which would later lay the foundation for the new field of game theory as a mathematical discipline. The minimax theorem may be summarized as follows:

The Minimax Theorem (von Neumann, 1928)
The minimax theorem provides the conditions that guarantee that the max-min inequality is also an equality, i.e. that every finite, zero-sum, two-person game has optimal mixed strategies.

The proof was published in Zur Theorie der Gesellschaftsspiele (“On the Theory of Games of Strategy”) in 1928. In collaboration with economist Oskar Morgenstern, von Neumann later published the definitive book on such cooperative, zero-sum games, Theory of Games and Economic Behavior (1944).

Left: von Neumann, J. (1928). Zur Theorie der Gesellschaftsspiele (“On the Theory of Games of Strategy”). Right: First edition copy of Theory of Games and Economic Behavior (1944) by John von Neumann and Oskar Morgenstern (Photo: Whitmore Rare Books).
By the end of 1929, von Neumann’s number of published major papers had risen to 32, averaging almost one major paper per month. In 1929 he briefly became a Privatdozent at the University of Hamburg, where he found the prospects of becoming a professor to be better.

Quantum mechanicsIn a shortlist von Neumann himself submitted to the National Academy of Sciences later in his life, he listed his work on quantum mechanics in Göttingen (1926) and Berlin (1927–29) as the “most essential”. The term quantum mechanics, largely devised by Göttingen’s own twenty-three year old wunderkind Werner Heisenberg the year before was still hotly debated, and in the same year von Neumann arrived, Erwin Schrödinger, then working from Switzerland, had rejected Heisenberg’s formulation as completely wrong (Macrae, 1992). As the story goes:

"In Johnny's early weeks at Göttingen in 1926, Heisenberg lectured on the difference between his and Schrödinger's theories. The aging Hilbert, professor of mathematics, asked his physics assistant, Lothar Nordheim, what on earth this young man Heisenberg was talking about. Nordheim sent to the professor a paper that Hilbert still did not understand. To quote Nordheim himself, as recorded in Heims's book: "When von Neumann saw this, he cast it in a few days into elegant axiomatic form, much to the liking of Hilbert." To Hilbert's delight, Johnny's mathematical exposition made much use of Hilbert's own concept of Hilbert space."- Excerpt, John von Neumann by Norman Macrae (1992)

Starting with the incident above, in the following years, von Neumann published a set of papers which would establish a rigorous mathematical framework for quantum mechanics, now known as the Dirac-von Neumann axioms. As Van Hove (1958) writes,

"By the time von Neumann started his investigations on the formal framework of quantum mechanics this theory was known in two different mathematical formulations: the "matrix mechanics" of Heisenberg, Born and Jordan, and the "wave mechanics" of Schrödinger. The mathematical equivalence of these formulations had been established by Schrödinger, and they had both been embedded as special cases in a general formalism, often called "transformation theory", developed by Dirac and Jordan.This formalism, however, was rather clumsy and it was hampered by its reliance upon ill-defined mathematical objects, the famous delta-functions of Dirac and their derivatives. [..] [von Neumann] soon realized that a much more natural framework was provided by the abstract, axiomatic theory of Hilbert spaces and their linear operators."- Excerpt, Von Neumann's Contributions to Quantum Theory by Léon Van Hove (1958)

In the period from 1927–31, von Neumann published five highly influential papers relating to quantum mechanics:

von Neumann (1927)

Mathematische Begründung der Quantenmechanik

von Neumann (1927)

Wahrscheinlichkeitstheoretischer Aufbau der Quantenmechanik

von Neumann (1927)

Thermodynamik quantenmechanischer Gesamtheiten

von Neumann (1930)

Allgemeine Eigenwerttheorie Hermitescher Funktionaloperatoren

von Neumann (1931)

Die Eindeutigkeit der Schrödingerschen Operatoren

His basic insight, which neither Heisenberg, Bohr or Schrödinger had, in the words of Paul Halmos was “that the geometry of the vectors in a Hilbert space as the same formal properties as the structure of the states of a quantum mechanical system” (Macrae, 1992). That is, von Neumann realized that a state of a quantum system could be represented by the point of a complex Hilbert space, that in general, could be infinite-dimensional even for a single particle. In such a formal view of quantum mechanics, observable quantities such as position or momentum are represented as linear operators acting on the Hilbert space associated with the quantum system (Macrae, 1992). The uncertainty principle, for instance, in von Neumann’s system is translated into the non-commutativity of two corresponding operators.

Summarized, von Neumann’s contributions to quantum mechanics can be said to broadly be two-fold, consisting of:

The mathematical framework of quantum theory,

The statistical aspects of quantum theory.

First edition copy of Mathematische Grundlagen der Quantenmechanik (1932) by John von NeumannHis work on quantum mechanics was eventually collected in the highly influential 1932 book Mathematische Grundlagen der Quantenmechanik (“Mathematical Foundations for Quantum Mechanics”), considered the first rigorous and complete mathematical formulation of quantum mechanics.

Quantum mechanics was very fortunate indeed to attract, in the very first years after its discovery in 1925, the interest of a mathematical genius of von Neumann’s stature. As a result, the mathematical framework of the theory was developed and the formal aspects of its entirely novel rules of interpretation were analysed by one single man in two years (1927–1929). — Van Hove (1958)

Operator theoryFollowing his work in set theory and quantum mechanics, while still in Berlin, von Neumann next turned his attention to algebra, in particular operator theory which concerns the study of linear operators on function spaces. The most trivial examples are the differential and integral operators we all remember from calculus. von Neumann introduced the study of rings of operators through his invention of what is now known as von Neumann algebras, defined as

Definition of a von Neumann algebra
A von Neumann algebra is a *-algebra of bounded operators on a Hilbert space that is closed in the weak operator topology and contains the identify operator

The work was published in the paper Zur Algebra der Funktionaloperationen und Theorie der normalen Operatoren (“On the Algebra of Functional Operations and Theory of Normal Operators”) in 1930.

In AmericaJohn von Neumann first travelled to America while still a Privatdozent at the University of Hamburg in October 1929 when he was invited to lecture on quantum theory at Princeton University. The visit led to an invitation to return as a visiting professor, which he did in the years 1930–33. The same year this tenure finished, Adolf Hitler first came to power in Germany, leading von Neumann to abandon his academic posts in Europe altogether, stating about the Nazi regime that

“If these boys continue for two more years, they will ruin German science for a generation — at least”

By most accounts, of course, von Neumann’s prediction turned out true. The following year, when asked by the Nazi minister of education “How mathematics is going at Göttingen, now that it is free from the Jewish influence?” Hilbert is said to have replied:

“There is no mathematics in Göttingen anymore.”

At Princeton University (1930–1933)The circumstances under which von Neumann (and a plethora of other first-rate mathematicians and physicists) would find themselves in Princeton, New Jersey in the mid-1930s is by now well known.

In the case of von Neumann in particular, he was recruited alongside his Lutheran high school contemporary Eugene Wigner by Princeton University professor Oswald Veblen, on a recommendation from Princeton, according to Wigner (Macrae, 1992) to:

"..invite not a single person but at least two, who already knew each other, who wouldn't suddenly feel put on an island where they had no intimate contact with anybody. Johnny's name was of course well known by that time the world over, so they decided to invite Johnny von Neumann. They looked: who wrote articles with John von Neumann? They found: Mr. Wigner. So they sent a telegram to me also."- Excerpt, John von Neumann by Norman Macrae (1992)

And so von Neumann first came to Princeton in 1930 as a visiting professor. Regarding his work while there, von Neumann himself later in life especially highlighted his work on ergodic theory.

Ergodic theoryErgodic theory is the branch of mathematics that studies the statistical properties of deterministic dynamical systems. Formally, ergodic theory is concerned with the states of dynamical systems with an invariant measure. Informally, think of how the planets move according to Newtonian mechanics in a solar system: the planets move but the rule governing the planets’ motion remains constant. In two papers published in 1932, von Neumann made foundational contributions to the theory of such systems, including the von Neumann’s mean ergodic theorem, considered the first rigorous mathematical basis for the statistical mechanics of liquids and gases. The two papers are titled Proof of the Quasi-ergodic Hypothesis (1932) and Physical Applications of the Ergodic Hypothesis (1932).

A subfield of measure theory, ergodic theory in other words concerns the behavior of dynamical systems which are allowed to run for a long time. von Neumann’s ergodic theorem is one of the two most important theorems in the field, the other being by Birkhoff (1931). According to Halmos (1958)

"The profound insight to be gained from [von Neumann's] paper is that the whole problem is essentially group-theoretic in character, and that, in particular, for the solvability of the problem of measure the ordinary algebraic concept of solvability of a group is relevant. Thus, according to von Neumann, it is the change of group that makes a difference, not the change of space; replacing the group of rigid motions by other perfectly reasonable groups we can produce unsolvable problems in R2 and solvable ones in R3."- Excerpt, Von Neumann on Measure and Ergodic Theory by Paul R. Halmos (1958)

“If von Neumann had never done anything else, they would have been sufficient to guarantee him mathematical immortality” — Paul Halmos (1958)

At the Institute for Advanced StudyFollowing his three-year stay as a visiting professor at Princeton in the period 1930–33, von Neumann was offered a lifetime professorship on the faculty of the Institute for Advanced Study (IAS) in 1933. He was 30 years old. The offer came after the the institute’s plan to appoint von Neumann’s former professor Hermann Weyl fell through (Macrae, 1992). Having only been founded three years prior, von Neumann became one of the IAS’ first six professors, the others being J. W. Alexander, Albert Einstein, Marston Morse, Oswald Veblen and eventually, Hermann Weyl.

Institute for Advanced Study in Princeton, New Jersey (Photo: Cliff Compton)When he joined in 1933, the Institute was still located in the math department of Princeton University’s Fine Hall. Founded in 1930 by Abraham Flexner and funded by philanthropy money from Louis Bamberger and Caroline Bamberger Fuld, the Institute for Advanced Study was and is still a university unlike any other. Inspired by Flexner’s experiences at Heidelberg University, All Souls College, Oxford and the Collège de France, the IAS has been described as

“ A first-rate research institution with no teachers, no students, no classes, but only researchers protected from the vicissitudes and pressures of the outside world.” — Sylvia Nasar (1998)

In 1939 moved to its own campus and common room Fuld Hall, the Institute for Advanced Study in a matter of a few years in the early 1930s effectively inherited the University of Göttingen’s throne as the foremost center of the mathematical universe. The dramatic and swift change has since become known as the “Great Purge” of 1933, as a number of top rate academics fled Europe, fearing for their safety. Among them, in addition to von Neumann and Wigner, of course was Einstein (1933), Max Born (1933), fellow Budapestians Leó Szilárd (1938) and Edward Teller (1933), as well as Edmund Landau (1927), James Franck (1933) and Richard Courant (1933), among others.

Left: Photo of part of the faculty at the Institute for Advanced Study, including its most famous resident Albert Einstein, and John von Neumann, visible in the background. Right: Julian Bigelow, Herman Goldstine, J. Robert Oppenheimer and John von Neumann in front of MANIAC, the Institute for Advanced Study computer.
GeometryWhile at the Institute for Advanced Study, von Neumann founded the field of continuous geometry, an analogue of complex projective geometry where instead of a dimension of a subspace being in a discrete set 0, 1, …, n, it can be an element of the unit interval [0,1].

A continuous geometry is a lattice L with the following properties:- L is modular
- L is complete
- The lattice operations satisfy a continuity property
- Every element in L has a complement
- L is irreducible, meaning the only elements with unique complements are 0 and 1

As with his result in ergodic theory, von Neumann published two papers on continuous geometry, one proving its existence and discussing its properties, and one providing examples:

von Neumann (1936)

Continuous geometry.

von Neumann (1936)

Examples of continuous geometries

The Manhattan Project (1937–1945)In addition to his academic pursuits, beginning in the mid to late 30s, von Neumann developed an expertise in the science of explosions, phenomena which are very hard to model mathematically. In particular, von Neumann became a leading authority on the mathematics of shaped charges, explosive charges shaped to focus the effect of the energy of an explosive.

By 1937, according to Macrae, von Neumann had decided for himself that war was clearly coming. Although obviously suited for advanced strategic and operations work, humbly he instead applied to become a lieutenant in the reserve of the ordnance department of the U.S.Army. As a member of the Officers’s Reserve Corps, this would mean that he could get trouble-free access to various sorts of explosion statistics, which he thought would be fascinating (Macrae, 1992).

Left: The photo from von Neumann’s Los Alamos ID badge. Right: John von Neumann talking with Richard Feynman and Stanislaw Ulam in Los Alamos (Photo: )
Needless to say, von Neumann‘s main contributions to the atomic bomb would not be as a lieutenant in the reserve of the ordnance department, but rather in the concept and design of the explosive lenses that were needed to compress the plutonium core of the Fat Man weapon that was later dropped on Nagasaki.

A member of the Manhattan Project in Los Alamos, New Mexico, von Neumann in 1944 showed that the pressure increase from explosion shock wave reflections from solid objects was greater than previously believed, depending on the angle of its incidence. The discovery led to the decision to detonate atomic bombs some kilometers above the target, rather than on impact (Macrae, 1992). von Neumann was present during the first Trinity test on July 16th, 1945 in the Nevada desert as the first atomic bomb test ever successfully detonated.

Work on philosophy

von Neumann speaking at the American Philosophical Society in 1957. Photo: Alfred EisenstaedtMacrae (1992) makes the point that in addition to being one of the foremost mathematicians in his lifetime, in many ways, von Neumann should perhaps also be considered one of his era’s most important philosophers. Professor of philosophy John Dorling at the University of Amsterdam, in particular, highlights in particular von Neumann’s contributions to the philosophy of mathematics (including set theory, number theory and Hilbert spaces), physics (especially quantum theory), economics (game theory), biology (cellular automata), computers and artificial intelligence.

His work on the latter two, computers and artificial intelligence (AI) occurred first while he was in Princeton in the mid 1930s meeting with the 24 year old Alan Turing first when the latter spent a year at the IAS in 1936–37. Turing began his career by working in the same field as von Neumann had — on working on set theory, logic and Hilbert’s Entscheidungsproblem. When he finished his Ph.D at Princeton in 1938, Turing had extended the work of von Neumann and Gödel and introduced ordinal logic and the notion of relative computing, augmenting his previously devised Turing machines with so-called oracle machines, allowing the study of problems that lay beyond the capabilities of Turing machines. Although inquired about by von Neumann for a position as a postdoctoral research assistant following his Ph.D., Turing declined and instead travelled back to England.(Macrae, 1992).

Work on computing

"After having been here for a month, I was talking to von Neumann about various kinds of inductive processes and evolutionary processes, and just as an aside he said, "Of course that's what Turing was talking about." And I said, "Who's Turing?". And he said, "Go look up Proceedings of the London Mathematical Society, 1937".The fact that there is a universal machine to imitate all other machines ... was understood by von Neumann and few other people. And when he understood it, then he knew what we could do." - Julian Bigelow"- Excerpt, Turing's Cathedral by George Dyson (2012)

Although Turing left, von Neumann continued thinking about computers throughout the end of the 30s and the war. Following his experiences working on the Manhattan Project, he was first drawn into the ENIAC project at the Moore School of Engineering at the University of Pennsylvania during the summer of 1944. Having observed the large amounts of calculation needed to predict blast radii, plan bomb paths and break encryption schemes, von Neumann early saw the need for substantial increases in computing power.

In 1945, von Neumann proposed a description for a computer architecture now known as the von Neumann architecture, which includes the basics of a modern electronic digital computer including:

A processing unit that contains an arithmetic logic unit and processor registers;A control unit that contains an instruction register and a program counterA memory unit that can store data and instructions;External storage; andInput and output mechanisms;

John von Neumann with the IAS machine, sometimes called the “von Neumann Machine”, stored in the the basement of Fuld Hall from 1942–1951 (Photo: Alan Richards)
The same year, in software engineering, von Neumann invented the so-called merge sort algorithm which divides arrays in half before sorting them recursively and then merging them. von Neumann himself wrote the first 23 page sorting program for the EDVAC computer in ink. In addition, in a pioneering 1953 paper entitled Probabilistic Logics and the Synthesis of Reliable Organisms from Unrealiable Components, von Neumann was first to introduce stochastic computing, though the idea was so groundbreaking that it could not be implemented for another decade or so (Petrovik & Siljak, 1962). Related, von Neumann created the field of cellular automata through his rigorous mathematical treatment of the structure of self-replication, which preceded the discovery of the structure of DNA by several years.

Although influential in his own right, throughout his life, von Neumann made sure to acknowledge that the central concept of the modern computer was indeed Turing’s 1936 paper On Computable Numbers, with an Application to the Entscheidungsproblem (Fraenkel, 1972)

”von Neumann firmly emphasised to me, and to others I am sure, that the fundamental conception is owing to Turing — insofar as not anticipated by Babbage, Lovelace and others.” — Stanley Fraenkel (1972)

Consultancies

"The only part of your thinking we'd like to bid for systematically is that which you spend shaving: we'd like you to pass on to us any ideas that come to you while so engaged."Excerpt, Letter from the Head of the RAND Corporation to von Neumann (Poundstone, 1992)

Throughout his career in America, von Neumann held a number of consultancies for various private, public and defense contractors including the National Defense Research Council (NDRC), the Weapons Systems Evaluation Group (WSEG), the Central Intelligence Agency (CIA), the Lawrence Livermore National Laboratory (LLNL) and the RAND Corporation, in addition to being an advisor to the Armed Forces Specials Weapons Project, a member of the General Advisory Committee of the Atomic Energy Commission, of the Scientific Advisory Group of the United States Air Force and in 1955 a commissioner of the Atomic Energy Commission (AEC).

PersonalityDespite his many appointments, responsibilities and copious research output, von Neumann lived a rather unusual lifestyle for a mathematician. As described by Vonnauman and Halmos:

“Parties and nightlife held a special appeal for von Neumann. While teaching in Germany, von Neumann had been a denizen of the Cabaret-era Berlin nightlife circuit.” — Vonneuman (1987)

The parties at the von Neumann’s house were frequent, and famous, and long. — Halmos (1958)

John von Neumann with his wife Klari Dan and their dog (Photo: Alan Richards)

His first wife, Klara, said that he could count everything except calories.

von Neumann also enjoyed Yiddish and dirty jokes, especially limericks (Halmos, 1958). He was a non-smoker, but at the IAS received complaints for regularly playing extremely loud German march music on the gramophone in his office, distracting those in neighboring offices, including Albert Einstein. In fact, von Neumann claimed to do some of his best work in noisy, chaotic environments such as in the living room of his house with the television blaring. Despite being a bad driver, he loved driving, often while reading books, leading to various arrests and accidents.

Von Neumann in the Florida Everglades in 1938 (Photo: Marina von Neumann Whitman)As a thinkerStanislaw Ulam, one of von Neumann’s close friends, described von Neumann’s mastery of mathematics as follows:

“Most mathematicians know one method. For example,  Norbert Wiener had mastered Fourier transforms. Some mathematicians have mastered two methods and might really impress someone who knows only one of them. John von Neumann had mastered three methods: 1) A facility for the symbolic manipulation of linear operators, 2) An intuitive feeling for the logical structure of any new mathematical theory; and 3) An intuitive feeling for the combinatorial superstructure of new theories.”

Biographer Sylvia Nasar describes von Neumann’s own “thinking machine” by the following, now well-known anecdote regarding the so-called “ two trains puzzle”:

Two bicyclists start twenty miles apart and head toward each other, each going at a steady rate of 10 m.p.h. At the same time, a fly that travels at a steady 15 m.p.h. starts from the front wheel of the southbound bicycle and flies to the front wheel of the northbound one, then turns around and flies to the front wheel of the southbound one again, and continues in this manner till he is crushed between the two front wheels. Question: what total distance did the fly cover?There are two ways to answer the problem. One is to calculate the distance the fly covers on each leg of its trips between the two bicycles and finally sum the infinite series so obtained. The quick way is to observe that the bicycles meet exactly an hour after they start so that the fly had just an hour for his travels; the answer must therefore be 15 miles. When the question was put to von Neumann, he solved it in an instant, and thereby disappointed the questioner: “Oh, you must have heard the trick before!” “What trick,” asked von Neumann, “all I did was sum the infinite series.”Excerpt, A Beautiful Mind (Nasar, 1998)

As a supervisor

In the paper Szeged in 1934 (Lorch, 1993) Edgar R. Lorch describes his experience of working as an assistant for von Neumann in the 1930s, including his duties:

Attending von Neumann’s lectures on operator theory, taking notes, completing unfinished proofs and circulating them to all American university libraries;Assisting von Neumann in his role as the editor of the Annals of Mathematics by reading through every manuscript accepted to the publication, underlining greek letters in red and german letters in green, circling italics, writing notes to printers in the margins and going once per week to the printers in order to instruct them in the art of typesetting;Translating von Neumann’s numerous 100-page papers into English;

"His fluid line of thought was difficult for those less gifted to follow. He was notorious for dashing out equations on a small portion of the available blackboard and erasing expressions before students could copy them."- Excerpt, John von Neumann: As Seen by his Brother by N.A. Vonneuman (1987)

Later years

President Dwight D. Eisenhower (left) presenting John von Neumann (right) the Presidential Medal of Freedom in 1956In 1955, Von Neumann was diagnosed with what was likely either bone, pancreatic or prostate cancer (accounts differ on which diagnosis was made first). He was 51 years old. Following two years of illness which at the end confined him to a wheelchair, he eventually died on the 8th of February 1957, at 53 years old. On his deathbed, he reportedly entertained his brother by reciting the first few lines of each page from Goethe’s Faust, word-for-word, by heart (Blair, 1957).

He is buried at Princeton Cemetery in Princeton, New Jersey alongside his lifelong friends Eugene Wigner and Kurt Gödel. Gödel wrote him a letter a year before his death, which has been made public. The letter is discussed in detail by Hartmanis (1989) in his working paper The Structural Complexity Column. An excerpt is included below:

Letter from Kurt Gödel to von Neumann, March 20th 1956Dear Mr. von Neumann:
With the greatest sorrow I have learned of your illness. The news came to me as quite unexpected. Morgenstern already last summer told me of a bout of weakness you once had, but at that time he thought that this was not of any greater significance. As I hear, in the last months you have undergone a radical treatment and I am happy that this treatment was successful as desired, and that you are now doing better. I hope and wish for you that your condition will soon improve even more and that the newest medical discoveries, if possible, will lead to a complete recovery.[...]I would be very happy to hear something from you personally. Please let me know if there is something that I can do for you. With my best greetings and wishes, as well to your wife,Sincerely yours,
Kurt GödelP.S. I heartily congratulate you on the award that the American government has given to you

Interview on TelevisionRemarkably, there exists a video interview with von Neumann on the NBC show America’s Youth Wants to Know in the early 1950s (below):

For anyone interested in learning more about the life and work of John von Neumann, I especially recommend his friend Stanislaw Ulam’s 1958 essay John von Neumann 1903–1957 in the Bulletin of the American Mathematical Society 64 (3) pp 1–49 and the book John von Neumann* by Norman Macrae (1992).

This essay is part of a series of stories on math-related topics, published in Cantor’s Paradise, a weekly Medium publication. Thank you for reading!

[FJB] All C++20 core language features with examples Apr 2, 2021 ...

FJB — 4/7/2021 11:09:31 AM

All C++20 core language features with examples Apr 2, 2021

Introduction The story behind this article is very simple, I wanted to learn about new C++20 language features and to have a brief summary for all of them on a single page. So, I decided to read all proposals and create this “cheat sheet” that explains and demonstrates each feature. This is not a “best practices” kind of article, it serves only demonstrational purpose. Most examples were inspired or directly taken from corresponding proposals, all credit goes to their authors and to members of ISO C++ committee for their work. Enjoy!

Table of contents

Concepts
Modules
Coroutines
Three-way comparison
Lambda expressions
- Allow lambda-capture [=, this]
- Template parameter list for generic lambdas
- Lambdas in unevaluated contexts
- Default constructible and assignable stateless lambdas
- Pack expansion in lambda init-capture
Constant expressions
- Immediate functions(consteval)
- constexpr virtual function
- constexpr try-catch blocks
- constexpr dynamic_cast and polymorphic typeid
- Changing the active member of a union inside constexpr
- constexpr allocations
- Trivial default initialization in constexpr functions
- Unevaluated asm-declaration in constexpr functions
- std::is_constant_evaluated()
Aggregates
- Prohibit aggregates with user-declared constructors
- Class template argument deduction for aggregates
- Parenthesized initialization of aggregates
Non-type template parameters
- Class types in non-type template parameters
- Generalized non-type template parameters
Structured bindings
- Lambda capture and storage class specifiers for structured bindings
- Relaxing the structured bindings customization point finding rules
- Allow structured bindings to accessible members
Range-based for loop
- init-statements for range-based for loop
- Relaxing the range-based for loop customization point finding rules
Attributes
- [[likely]] and [[unlikely]]
- [[no_unique_address]]
- [[nodiscard]] with message
- [[nodiscard]] for constructors
Character encoding
- char8_t
- Stronger Unicode requirements
Sugar
- Designated initializers
- Default member initializers for bit-fields
- More optional typename
- Nested inline namespaces
- using enum
- Array size deduction in new-expressions
- Class template argument deduction for alias templates
constinit
Signed integers are two’s complement
__VA_OPT__ for variadic macros
Explicitly defaulted functions with different exception specifications
Destroying operator delete
Conditionally explicit constructors
Feature-test macros
Known-to-unknown bound array conversions
Implicit move for more local objects and rvalue references
Conversion from T* to bool is narrowing
Deprecate some uses of volatile
Deprecate comma operator in subscripts
Fixes
- Initializer list constructors in class template argument deduction
- const&-qualified pointers to members
- Simplifying implicit lambda capture
- const mismatch with defaulted copy constructor
- Access checking on specializations
- ADL and function templates that are not visible
- Specify when constexpr function definitions are needed for constant evaluation
- Implicit creation of objects for low-level object manipulation

[FJB] Predictive Coding has been Unified with Backpropagation - LessWrong ...

FJB — 4/5/2021 4:55:01 PM

Predictive Coding has been Unified with Backpropagation - LessWrong

lesswrong.com

Artificial Neural Networks (ANNs) are based around the backpropagation algorithm. The backpropagation algorithm allows you to perform gradient descent on a network of neurons. When we feed training data through an ANNs, we use the backpropagation algorithm to tell us how the weights should change.

ANNs are good at inference problems. Biological Neural Networks (BNNs) are good at inference too. ANNs are built out of neurons. BNNs are built out of neurons too. It makes intuitive sense that ANNs and BNNs might be running similar algorithms.

There is just one problem: BNNs are physically incapable of running the backpropagation algorithm.

We do not know quite enough about biology to say it is impossible for BNNs to run the backpropagation algorithm. However, "a consensus has emerged that the brain cannot directly implement backprop, since to do so would require biologically implausible connection rules" [1].

The backpropagation algorithm has three steps.

Flow information forward through a network to compute a prediction.
Compute an error by comparing the prediction to a target value.
Flow the error backward through the network to update the weights.

The backpropagation algorithm requires information to flow forward and backward along the network. But biological neurons are one-directional. An action potential goes from the cell body down the axon to the axon terminals to another cell's dendrites. An axon potential never travels backward from a cell's terminals to its body.

Hebbian theory Predictive coding is the idea that BNNs generate a mental model of their environment and then transmit only the information that deviates from this model. Predictive coding considers error and surprise to be the same thing. Hebbian theory is specific mathematical formulation of predictive coding.

Predictive coding is biologically plausible. It operates locally. There are no separate prediction and training phases which must be synchronized. Most importantly, it lets you train a neural network without sending axon potentials backwards.

Predictive coding is easier to implement in hardware. It is locally-defined; it parallelizes better than backpropagation; it continues to function when you cut its substrate in half. (Corpus callosotomy is used to treat epilepsy.) Digital computers break when you cut them in half. Predictive coding is something evolution could plausibly invent.

Unification The paper Predictive Coding Approximates Backprop Along Arbitrary Computation Graphs [1:1] "demonstrate[s] that predictive coding converges asymptotically (and in practice rapidly) to exact backprop gradients on arbitrary computation graphs using only local learning rules." The authors have unified predictive coding and backpropagation into a single theory of neural networks. Predictive coding and backpropagation are separate hardware implementations of what is ultimately the same algorithm.

There are two big implications of this.

This paper permanently fuses artificial intelligence and neuroscience into a single mathematical field.
This paper opens up possibilities for neuromorphic computing hardware.

available on arxiv

[FJB] I FIND IT HARD TO GO BACK TO HEAVY WEIGHT IDEs AFTER VS CODE... archive.vn Ref...

FJB — 3/6/2021 4:40:06 PM

I FIND IT HARD TO GO BACK TO HEAVY WEIGHT IDEs AFTER VS CODE...

archive.vn

Reflections on IDEA vs VS Code

The story of IDEA vs VS Code is a story of low-end disruption, straight from the textbook. There is an emergent competitior that is not yet feature-rich but it is not elephantine yet and its technology has an unique advantage. The key technology here is probably the Language Server Protocol; it offloads programming language related smarts directly to the compiler (typically), thus relieving the IDE from supporting a hundred programming languages with all their warts and twists. As the compiler is the ultimate authority on the matters of language, that seems like a wise move: reusing instead of reimplementing. The other technology is Electron and, by extension, a browser engine based GUI. Given how much money was put into browsers, that is probably the most mature multiplatform GUI framework in existence.
That situation may catch the IDEA family between a rock and a hard place: it has to outdo compilers on one side and browser engines on the other side. Specifically, in their primary line of business. Which may easily become an unwinnable bet.
So far it looked like textbook low-end disruption, except for one thing: the disruptor is an old fat incumbent while the disrupted party is a (relatively) young emergent competitor. That is the funny part. Clearly, the MS leadership has read the book.
What bothers me about JetBrains is the fact that they seem to be playing along. Judging by the talks on their recent conference, IDEA goes more elephantine, more corporate, more complex. That is easy to understand: a corporate user pays a lot. But, that is the classic low-end disrupted trajectory that leads to the very same corner where IBM DB2 sits. They will retain some deep pocketed customers, but all the interesting things will be happening somewhere else.
In this regard I will mention two announcements: the CodeWithMe technology and a lightweight "IDEA viewer" product. CodeWithMe allows one IDEA instance to run another instance remotely to allow for collaborative work. Even the color scheme and the shortcuts are provided by the master instance, if I understood that correctly. That is very Java and very corporate, no doubt. The IDEA viewer is another step in the same direction: let the IDE run somewhere else, maybe on a server, and let people use a lightweight client "on a laptop in a cafe". I seriously doubt it will work well in an average cafe though. Their WiFi tends to be unreliable. Given this degree of dependence of the client machine, spotty WiFi will cause a developer to smash his laptop against the coffee machine. Then, the developer will have to pay for both. I experienced similar issues with JetBrains YouTrack in the past: it was an awesome issue tracker, unless you use a poor connection or the server is too far away. Then, it was unnerving. So I assume, that will be stress-free on a wired connection only. Whether the developer is using a laptop or a workstation is of secondary importance then: it is wired. Still, that feature fits some corporate behavior patterns, so it may entrench IDEA better in that environment.
In addition to the rock and the hard place, IDEA seems to be caught in one more aspect. GitHub is now a MS property, so in the future VS Code is expected to be more and more integrated into GitHub. That pretty much catches all the young and hip audience in a MS owned behavior loop. Which certainly shows some very competent strategic planning. Meanwhile, JetBrains seems to be staying afloat mostly thanks to hard work and sheer luck.

[jroberts] $IDEX - GREEN Act: US Democrats to push EV sales cap + E-BIKE ActThere is also l...

jroberts — 3/5/2021 1:46:46 PM

$IDEX - GREEN Act: US Democrats to push EV sales cap + E-BIKE ActThere is also legislation on the table to introduce tax credits for electric bicycles.https://www.electrive.com/2021/02/12/green-act-us-democrats-to-push-ev-sales-cap-e-bike-act/

https://ideanomics.com/

[FJB] INTERESTING TO FORMER C PROGRAMMERS. LIST OF BANNED C FUNCTIONS AT MICROSOFT/GI...

FJB — 3/5/2021 11:23:32 AM

INTERESTING TO FORMER C PROGRAMMERS. LIST OF BANNED C FUNCTIONS AT MICROSOFT/GIT...

#ifndef BANNED_H

#define BANNED_H

* This header lists functions that have been banned from our code base,

* because they're too easy to misuse (and even if used correctly,

* complicate audits). Including this header turns them into compile-time

* errors.

#define BANNED(func) sorry_##func##_is_a_banned_function

#undef strcpy

#define strcpy(x,y) BANNED(strcpy)

#undef strcat

#define strcat(x,y) BANNED(strcat)

#undef strncpy

#define strncpy(x,y,n) BANNED(strncpy)

#undef strncat

#define strncat(x,y,n) BANNED(strncat)

#undef sprintf

#undef vsprintf

#ifdef HAVE_VARIADIC_MACROS

#define sprintf(...) BANNED(sprintf)

#define vsprintf(...) BANNED(vsprintf)

#else

#define sprintf(buf,fmt,arg) BANNED(sprintf)

#define vsprintf(buf,fmt,arg) BANNED(vsprintf)

#endif

#undef gmtime

#define gmtime(t) BANNED(gmtime)

#undef localtime

#define localtime(t) BANNED(localtime)

#undef ctime

#define ctime(t) BANNED(ctime)

#undef ctime_r

#define ctime_r(t, buf) BANNED(ctime_r)

#undef asctime

#define asctime(t) BANNED(asctime)

#undef asctime_r

#define asctime_r(t, buf) BANNED(asctime_r)

#endif /* BANNED_H */

[FJB] TSMC at the head of history’s tide: two high walls and one sharp knife docs.goo...

FJB — 3/4/2021 9:48:52 AM

TSMC at the head of history’s tide: two high walls and one sharp knife

docs.google.com

*Note: This is a joint translation by Joy Dantong Ma and Jeffrey Ding -- all credit for the original goes to the authors and the original text linked below. These are informal translations and all credit for the original work goes to the authors. Others are welcome to share excerpts from these translations as long as my original translation is cited. Commenters should be aware that the Google Doc is also publicly shareable by link. These translations are part of the ChinAI newsletter - weekly-updated library of translations from Chinese thinkers on AI-related issues: chinai.substack.com

________________________________________________________________________________

Author: ?? Chen Shuai, senior analyst

Source: ????? (Yuanchuan research group) -- have never heard of them

Editors: ???/??? (Dai Laoban -- we have covered in a previous translation)

Date: May 31, 2020

Original Mandarin: ?????????:????,????

Introduction

In December 1989, Taipei's cold rain was drizzling, and Samsung head Lee Kun-hee (???) went to Taiwan for a study trip. He secretly invited Morris Chang (Chinese: ???/Morris Chang [a] [c] [d]), the founder of TSMC, to have breakfast for one purpose: to poach the 58-year-old veteran.

At this time, TSMC has been silently established for two years, and it is still unknown in the industry. Its “foundry” model was not the mainstream approach of the chip field at that time, and people couldn’t understand it. In 1987 when TSMC was founded, Samsung founder Lee Byung-chul (???) passed away, and his third son, Lee Kun-hee, took charge of Samsung. As soon as he took office, he shouted the slogan "Start-up Again (????)" and made a foray into electronics and semiconductors.

Morris Chang is the talent that Lee Kun-hee badly needs. In 1983, he stepped back from the position of "third-in-command" of Texas Instruments. Although he could just enjoy the American dream of "one house, two cars, three dogs,” he was always unwilling. So two years later, when Sun Yun-suan, "Chiang Ching-kuo's successor," invited him to take up the post of president of the Industrial Technology Research Institute in Taiwan, Morris Chang decided to risk it and get out of his comfort zone.

Morris Chang grew up on the mainland and left in 49. He went to the United States to study and work for more than 30 years. He is not familiar with Taiwan, but he can't stand the temptation of “being the top figure” (??????). Only one year after arriving in Taiwan, Morris Chang, 56, decided to go wild again: start a business and become a company that specializes in manufacturing for other chip companies. This model was not favored by peers and investors at the time.

At the dinner table, Lee Kun-hee broke it down: Semiconductors require a lot of capital and talent, and the risks are also great. Samsung is currently developing well. He wanted Morris Chang to come to the Samsung factory and take a look. Lee Kun-hee's words embodied his admiration and sympathy for Zhang, similar to when Cao Cao looked at Liu Bei and said, "?????? (only us two are the strongest)," he wished that Morris Chang would immediately elope with him to Seoul.

Morris Chang was now struggling to get sales/orders, but he was tired of being second and third, and he firmly refused Samsung. Lee Kun-hee did not give up, and invited him to visit Samsung. Morris Chang readily accepted, and after visiting the factory for half a day, he even praised Samsung's production capacity as "impressive", but still refused to leave TSMC. Seeing his firm attitude, Lee Kun-hee had to give up.

After parting ways this time, the trajectory of the two would continue to intersect: TSMC and Samsung have each followed their own routes to rise to become global semiconductor giants, and then launched a bloody duel. At the peak, both sides threw money around, eyes blood-red, and once bought 40% of the world's semiconductor manufacturing equipment. This is both a business war between the two companies and a path to industrial upgrading for these two regions that they had no alternative for.

For quite a long time in the past, and for a long time in the future, TSMC's biggest rival is Samsung, not SMIC.

Part I. Overtaking: From the edge of the industry to the center of the stageAlthough TSMC is a Taiwanese company, Morris Chang injects the "American soul" into it: the management experience from his time at Texas Instruments, IBM-licensed technology, and a large number of talents returning from the United States.

For example, Hu Chenming (???/Calvin Hu), the first technology executive of TSMC, is a professor at the University of California, Berkeley, and his favorite pupil Liang Mong-Song (???) also switched from AMD to TSMC; R&D team leader Chiang Shang-Yi (???) previously worked in Texas Instruments and HP; Cai Lixing (???/Rick Tsai), who later took over for Morris Chang as CEO, was a PhD graduate from Cornell; Yu Zhenhua (???/Douglas Yu), a core technical figure, also had a PhD. from Georgia Institute of Technology.

TSMC received not only talents but also orders for goods from the United States. The semiconductor industry originated in the United States, and then began to transfer to Japan. As a result, Japanese semiconductor companies have cultivated very strong battle-tested competencies, and in the field of memory chips, relying on shrewd management and cost advantages, had utterly routed American companies. In the late 1980s, six of the world's top ten semiconductor companies were Japanese companies.

If you can’t beat them, change the race track. Thus, the United States withdrew from memory chips and made efforts in logic chips such as CPUs. Unlike the strong requirements for integration in memory chips, the design and production segments of logic chips could be separated, which brings opportunities for TSMC. In 1988, Intel sent the first large order and gave guidance on more than 200 processes, which can be described as "funding to get you on top of the horse and technology to take you far along the ride." [e]

Of course, these benefits were not given in vain. Feedbacks from the fast-growing TSMC redounded to the US semiconductor industry. Because they no longer had to bear the huge costs of independently building fabs, a large number of start-up chip design companies could pack lightly for battle and develop rapidly. American chip companies regained the commanding heights of the global chip industry. Today’s giants such as Qualcomm, NVIDIA, Marvell, etc. all benefited from thi [f]s.

In 1995, Nvidia founder Jensen Huang (???) encountered a commercial bottleneck, so he wrote to Morris Chang for help. Soon, he received a call in his noisy office from Morris. Jensen excitedly said to the people around him: Quiet! Morris called me. Subsequently, TSMC successfully completed Nvidia's order, helping it quickly occupy the market.

Jensen Huang was very moved by this, and had this experience captured in a comic which he gave to Morris Chang [2] [g].

[h]

Although TSMC was finding its wings and its model had gotten recognition from industry, its technology was licensed from IBM, and its (technological) autonomy was lacking, so it was still considered by Silicon Valley companies to be a second-rate company. Morris Chang was reluctant to become a technological vassal of the United States and had been waiting for the opportunity to become the master of his own fate. Finally, the opportunity came, and it came twice: i) a counterattack in copper interconnect technology, ii) a breakthrough in lithography machines.

The counterattack in copper interconnect technology ended IBM's technological hegemony: In 2003, IBM hoped to sell its newly developed copper interconnect technology to TSMC, but Morris Chang believed that IBM’s tech was not mature, and TSMC could do better itself. It was Chiang Shang-Yi who led the team to develop and fully utilize the process management experience learned at Texas Instruments: In order to prevent contaminating the materials, the R&D personnel had to strictly follow the route drawn on the floor even when walking.

More than a year later, TSMC's copper interconnect technology made the lead breakthrough, and it was six people who played a central role: Yu Zhenhua, Liang Mong-Song, Sun Yuancheng, Chiang Shang-Yi, Yang Guanglei, Lin Benjian. IBM's technology had not yet made it out of the laboratory. IBM's technological hegemony in foundries was ended. Ten years later, IBM paid another 1.5 billion US dollars, transferred the foundry business to GlobalFoundries [j] [k], and completely withdrew from this field.

As for the breakthrough in lithography machines, it not only gave TSMC a technological overtaking, but it also helped cultivate a solid equipment ally: In 2004, TSMC decided to develop wet lithography technology through a new method, and the initiator of this technological project, Lin Benjian, also comes from IBM.

This technology runs counter to the dry method scheme at the time, and Lin Benjian was mocked as "standing in the way of an aircraft carrier [l]." The Japanese "lithography machine overlords" Canon and Nikon also resisted the plan. Only the Dutch small factory ASML was willing to try it. In the end, TSMC completed a technological breakthrough, and ASML also quickly rose, becoming an industry giant and defeating Japanese hegemony, and forming a deep friendship with TSMC. [m]

Today, ASML is under the heavy pressure of the United States. This is a pain in the neck for SMIC, and it also limits Huawei's desire to find OEM partners.

Learning from the U.S. and then surpassing, these two “overtakings on a curve” showed that TSMC's foundry technology was extraordinary. In 2004, TSMC won half of the world's chip foundry orders, ranking in the top ten of the semiconductor industry in terms of scale. Ranked second is South Korea’s Samsung, which won 30% of the world’s market share by battling Japan to the death in memory chips, while Japan’s once-brilliant semiconductor industry only had three companies remaining in the top ten.

Seeing that the overall landscape had solidified, Morris Chang was eager to leave more time for his family. So in June 2005, Morris Chang announced his retirement as CEO and stepped back to an advisory post. He got off work exactly at 7 o'clock to accompany his family, eat dinner, and listen to concerts. At this time, his old friend Lee Kun-hee was gathering troops to prepare to enter the hinterland of TSMC. [n] [o]

Part II. Awakened: Lee Kun-hee Attacks, Morris Chang Returns to the FurnaceLee Kun-hee is the chief designer behind Samsung’s semiconductor division. In 1974, he proposed a plan (to set up this division) and went to the United States more than 50 times to bring back technology. This also moved his father Lee Byung-chul to declare that he must start this business before his eyes closed for the last time. However, in the face of Japan -- at the apex of its power -- in the 1980s, up to the death of Lee Byung-chul, Samsung Semiconductor lost 300 million US dollars, with no gain.

And in 1987 when Lee Kun-hee took over, the opportunity for Samsung Semiconductor finally came. That year, the secret of Japan’s Toshiba’s private sale of equipment to the Soviet Union was discovered by the United States. [p]The United States, which had been crushed by Japanese semiconductors, immediately took the opportunity to wield the sanctions stick. Not only did it impose a 100% tariff on Japanese memory chips, it also launched a "301" investigation that made many trading nations frightened. [q]

Thrilled and rejoicing at the news that Japanese semiconductors were being pressed to the ground by the United States, Samsung rushed over and also pressed its foot down.

The secret to Lee Kun-hee's success is "buy people at high prices and sell goods at low prices": he paid at triple their wages to hollow out Toshiba’s engineers, quickly upgraded Samsung’s technology, and then launched an offensive by selling at very low prices. He also played the “emotional” card, calling for overseas Korean engineers to return home and join the fray. Chae Dae Je, a technical backbone (key talent) who worked at IBM for 7 years, was swept up with excitement after hearing the call, and immediately returned to Korea to join the battle.

During the Asian financial crisis in 1997, Samsung still maintained high capital expenditures, dared to fight price wars, and used counter-cyclical investment methods to invest more even as it was losing more money. Finally, in 2004, it overwhelmed companies such as Toshiba of Japan and became the overlord of memory chips. Subsequently, Lee Kun-hee waved his hand, and directed his artillery fire to TSMC, thereby beginning a march on chip foundries.

Lee Kun-hee's strategy is very simple, take advantage of Samsung's diversified advantages, fan out from single points into a whole expanse, to break free from encirclement. For example, in facing Qualcomm, the largest customer of TSMC, Samsung adopted the method of "using purchasing to find selling opportunities," having Samsung phones buy Qualcomm chips, and then persuading Qualcomm to hand over the chip manufacturing to Samsung. For Apple, Samsung bundled together storage chips, display panels, and chip foundries in a sales strategy, the so-called strategy of “selling a cabbage and giving away some spring onions.”

Samsung's bundling strategy is a common way for semiconductor companies to develop business. For example, Qualcomm also uses the advantages of baseband processing to pair unsalable goods up with goods that sell well; AMD also sells CPUs and GPUs together. Samsung’s foundry revenue was only $75 million in 2006, but four years later it tripled, with A-series chips for Apple’s foundry accounting for 85%. It can be said that Samsung's chip division grew up by eating apples one by one.

In 2009, Samsung, which had a winning streak, held an internal meeting, and Lee Kun-hee’s eldest son, Lee [r] (Jae-yong), ambitiously announced a plan: Kill Taiwan, i.e., first eliminate Taiwan’s panel and memory chip industry, and then to defeat TSMC -- the Mount Everest in Taiwan -- to allow Samsung to completely dominate the advanced electronics industry and also to lay the foundation for his own succession to take over the power of his father.

It was only in 2013 that this plan was disclosed by Taiwan’s “New Weekly.” By then, Taiwan’s panel and memory chip industries were all chopped down by Samsung, leaving only TSMC.

Looking at the situation in 2009, it was not impossible for Samsung to defeat TSMC [3] [s]. At that time, TSMC's leaky house was suffering from continuous rain: after the 2009 financial crisis, profits fell sharply and it was forced to lay off workers. The chief architect of the layoffs was CEO Cai Lixing, who had been working for TSMC for nearly 20 years. He had done things calmly and had strong execution. He once led TSMC's first 8-inch fab, and was known as "a mini-Morris Chang".

Cai Lixing implemented a stricter performance evaluation system than in the Morris Chang era. For the bottom 5% of employees, per the evaluation, he canceled the previous observation period and directly announced layoffs. The fast cut to optimize costs was, in essence, a routine operation, but it angered people because it was not carried out in a humane way.

An employee who had worked for more than ten years and had received excellent rewards was thrown into the elimination list because he could not “996 [t]” since he needed to take care of his pregnant wife. This employee’s elderly father wrote a letter to Morris Chang in tears, urging the company not to lay off his son. Some people even posted banners on the door of Morris Chang’s house, accusing him for being dishonest. Embarrassed by this stain on his reputation, he hurriedly told his wife to send pastries and condolences.

At the same time, the yield rate of the company's new production line has not been improved, and customers have even cancelled orders. Morris Chang was anxious in his heart: the menacing Samsung was about to fight its way to his house gates, and Cai Lixing was still trying to show off his financial reporting skills in suppressing costs and increasing profits! In mid-June, TSMC held a board of directors meeting, and in less than ten minutes Morris Chang assigned Cai Lixing over to a photovoltaic department with less than ten people.

Then, the 78-year-old announced that he would return to the furnace, though he didn’t set a deadline.

After the return, Morris Chang did two things: he expanded the army and the equipment. He declared that the previous layoffs were invalid. Those who were willing to come back to work could immediately return to their posts, and he also invited the retired Chiang Shang-Yi to eat a meal in his office -- did not discuss salary or compensation -- and only gave an order for him to come back and spend the company’s new R&D budget increase of USD 1 billion as soon as possible.

In order to boost morale, Morris Chang even quoted Shakespeare's verse describing Henry V’s battle during his speech to TSMC employees: "Once more unto the breach, dear friends?" Henry V was regarded as a national hero by the British. He led a weak infantry force of less than 6,000 men and defeated the elite French troops that had six times the number of men. Morris Chang's referenced him for obvious reasons, in hopes that TSMC can also create a miracle of weak over strong.

The veteran took the lead, doing the work of two people. TSMC got customers to return and upgraded its technology. Especially in the key technology of the 28-nanometer process, Chiang Shang-Yi chose the gate-last scheme (high-k/metal gate -- HKMG) instead of the gate-first scheme (HKMG) that Samsung was developing. With correct judgment and strict process, the yield of TSMC greatly improved, whereas Samsung did not make progress.

However, at this time, Morris Chang did not unfurrow his eyebrows. He knew that to defeat Samsung and eliminate future troubles, the decisive point was not in Seoul but thousands of miles away on the West Coast of the United States, where there was a super customer that could support any foundry to get to the pinnacle of the world.

PART III. Uprising: Apple Fights Against Korea, TSMC Hands Over A Knife

In 2010, Morris Chang received a special guest at home: Apple's COO Jeff Williams. The two talked about building a factory over red wine, and after a long discussion, reached a cooperation agreement: Apple would order its entire generation of chips from TSMC, provided that TSMC secured US$9 billion in funding to build factories and 6,000 workers to ensure production capacity.

The meeting was much welcomed by both parties as Apple was struggling for air with Samsung’s hands on its neck. From 2008 to 2011, the global share of Samsung's smartphones increased 6 times, reaching 20%. However, more than half of Apple’s key parts needed to be purchased from Samsung. Apple gasped for air while gradually setting in motion a plan to replace Samsung as a supplier. In 2008, Apple shifted orders for flash memory chips from Samsung to Toshiba. Two years later, Apple diverted part of its screen order to Sharp.

In April 2011, Apple filed 16 accusations at one go against Samsung, alleging that Samsung's mobile phone plagiarized Apple’s. However, Samsung, who held Apple's lifeline of key component supplies, refused to surrender and immediately countered Apple’s claims. It accused Apple of infringing on 10 Samsung’s patents and demanded a complete stop of iPhone sales in the US. Apple was fighting in court with a hand on its neck and urged TSMC to accelerate its R&D. Chang sent out TSMC’s top troops at the year end of 2011 - “one team. ”

This team was composed of more than a hundred inter-departmental R&D engineers. They quietly flew to the US from Taipei, Hsinchu and other places and stationed at the Apple headquarters in Cupertino. Cupertino happens to be Hsinchu’s sister city and is less than 10 miles from Samsung and Apple’s courts. These engineers signed strict confidentiality agreements, and their secret task is to develop A8 chips with Apple, bypassing Samsung’s patents.

Since Samsung held many core patents, if TSMC used similar technologies, Samsung would sue TSMC until the latter went bankrupt. Therefore, this task had to be kept as a secret. Samsung was not shy about their plan either. Whenever they communicate with stock analysts, they would emphasize, “if TSMC dares to do so, we will sue them without a doubt.” In order to dispel Apple's concerns, TSMC first participated in the design of A6 chip to show its capabilities, and shared all of its own patents with Apple for verification without reservation.

In order to ensure success, TSMC specially developed two A8 versions for Apple to choose from, vowing to never stop until completely bypassing Samsung’s patent wall. At the same time, TSMC expanded its infrastructure at unprecedented speed and ramped up production capacity. Factory No.12 in Hsinchu, No.15 in Taichung and No.14 in Tainan were expanding at nearly three times the usual speed. Over the western coastline of Taiwan, planes transported chip manufacturing equipment from Europe, America and Japan non-stop.

Between 2011 and 2013, there were only three newly built ultra-large 12-inch foundries in the world, and TSMC alone built a new one and expanded two. In 2013, half of TSMC's revenue was poured into expansion. It wouldn’t be a stretch to say, Chang bet all his chips. Samsung, while not aware of the secret deal between Apple and TSMC, saw all of the expansion and came up with a plan.

Samsung contacted TSMC proactively, and expressed its intention to have TSMC manufacture Samsung’s 4G chip. The order was just a facade. What Samsung really hoped to achieve was to test TSMC’s technologies, process and production capacity. It was clear to Chang where Samsung’s real intention lay. Therefore, he asked Samsung to work with a Taiwanese chip design company, and then the design company could cooperate with TSMC. This way, there wouldn’t be any direct interaction between Samsung and TSMC. Samsung had to drop its plan.

In 2014, Apple finally announced the list of foundries for its A8 chip: TSMC was the one and only. The share price of TSMC soared, and the employees were relieved, "if it were not for the sense of honor and hope to defeat Samsung, who would want to be separated from their families for so long.” Taiwanese media reported with enthusiasm, “mobile phone saves Taiwan” [v], “Morris Chang unravels Samsung.”

But who would know, a few months later, a man who claimed to have TSMC in his blood, stood with Samsung and pushed TSMC to the edge of a cliff, yet again.

PART IV. Setbacks: Samsung Blessed with One General, TSMC Faced One Failure After Another.

Chang had a picture of his wife and himself in the office. The person who took the picture was one of Chang’s favorite pupils, Liang Mong-Song .

Liang was a student of TSMC’s first CTO, Chiang Shang-Yi, and a critical member during TSMC’s breakthrough in copper interconnect technology in 2002, ranking second in Taiwan authorities’ award list. He was the most promising candidate to succeed Chiang as director of R&D. However, just four months before Morris Chang returned in 2009, Liang handed in his resignation, and left TSMC after his 17-year tenure.

Liang did not leave TSMC because of poor performance; instead, he felt he was pushed out of the company. When Chiang retired in 2006, Liang considered himself the best successor in the company. What came next, however, was not a promotion, but an order to transfer him to lead a new initiative called “Beyond Moore [w] [x](‘s Law).” This plan sounded fancy, but had only a small office that could fit four people. It was later only implemented in two less-advanced foundries.

The office started to feel like an icebox for Liang. For more than eight months, he sat in the office alone, without stepping out or seeing colleagues. Liang felt embarrassed and insulted. But in fact the current CEO Wei Zhejia (???/Dr. C. C. Wei) also used to lead the “Beyond Moore” initiative. Wei started with one order after another, and eventually revived these two small factories. This “initiative” might have been a test to Liang from Morris Chang.

Whether it was an icebox or a test, Liang lost all hopes and decided to resign in February 2009. Liang taught at National Tsing Hua University for a few months after the resignation. Before long, he was introduced by his wife’s family (who are Korean) to teach telecommunication at Sungkyunkwan University. Two years later, Liang’s non-competition agreement expired, and he found a new employer - TSMC's old rival Samsung - as the technical lead of its semiconductor division.

Samsung had a thirst for talents like Liang. Liang’s annual salary was rumored to be as high as NT$135 million, tripling the standard amount at TSMC and even exceeding Samsung's co-CEO. Lee Kun-hee often said that three Bill Gates could elevate South Korea, and his task was to find three such geniuses. This kind of emphasis on talent regardless of cost is undoubtedly worth studying for mainland China 10 years later.

However, the gift from Samsung hadn’t been in Liang’s hands for three months, a cold complaint from TSMC arrived. The complaint was sternly worded, demanding that Liang stop divulging secrets and immediately resign from Samsung. Looking at the complaint, Liang might have wondered: shouldn’t there be no more contact from his previous employer?

TSMC filed the stern complaint because they noticed - Samsung had changed.

Morris Chang called Samsung a "300-pound gorilla" in the marketplace, but a “black dot in the radar” when it came to technology. However, since Liang’s resignation, Samsung seemed to have gotten a secret cookbook and achieved technology breakthroughs one after another every year: 45nm, 32nm, 28nm. In 2011, it was almost on par with TSMC. For the same catch-up, SMIC in mainland China spent more than 7 years.

Coincident or not, after some investigations, TSMC did find a lot of clues that Liang might have violated the non-compete agreement: The Sungkyunkwan University that Liang taught at is known as South Korea’s Tsinghua and is funded by Samsung; its campus is inside Samsung headquarters; the actual location of Liang’s classes was inside Samsung factory. In the past few years, whenever Liang traveled between Korea and Taiwan, it was all by Samsung’s private plane.

The thought of Liang violating his non-compete and working for Samsung enraged TSMC. Liang on the other hand also felt wronged by TSMC. In a courtroom that’s often confrational and combative, Liang poured out all of his sorrows.

Liang almost choked up and said [y], “based on my seniority, on what grounds did I get sent to a small unit that was so limiting? I felt deceived and insulted. The leadership at TSMC simply forgot about me. Why is TSMC so ruthless? For a person who has dedicated his life to TSMC, I hoped to once again fight for the TSMC but silence was the only response I received.”

He passionately continued, “I’m a man of my word, not a rebel who fled to the enemy’s camp like the media pictured. This narrative is a great insult to me and caused great harm to my family.”

Liang’s passionate demonstration of his frustration was moving. In the end, the judge ruled that Liang had resigned for two years, which had long passed the period of non-compete agreement. TSMC’s complaint was dismissed. TSMC was hit hard by the ruling, and before it could recover, another shock piled up. The Apple A9 chip order, which TSMC thought was a sure deal, went to Samsung. What scored this order for Samsung was an unmatched technology - the world's first 14nm FinFET process.

Hu Chenming is the inventor of FinFET and led TSMC’s effort to productionize FinFET. FinFET is a type of 3D transistors, a technology TSMC had been working on for nearly a decade. It was widely recognized as the key to unlock processes under 20nm. Hu’s favorite student was no others but Liang Mong-Song. Who could have known that Liang’s switch from TSMC to Samsung enabled the latter to jump ahead. It is just like the old saying – master taught the apprentice, only to be defeated and starved.

Taiwanese media regretfully commented, "the technical advantages of TSMC have been wiped out overnight."

After Apple turned to Samsung, Qualcomm followed suit and handed its latest chip OEM order to Samsung. When clients left, investors started to worry. Credit Suisse, who had been optimistic about TSMC for five consecutive years, gave a negative rating for the first time; Lyon Securities projected that TSMC would lose 80% of Apple's orders and more than $1 billion.

At the shareholders meeting in January 2015, Chang looked into the camera and admitted solemnly, "yes, we are a bit behind."

PART V. Counterattack: 100,000 youths, 100,000 livers

On the date Chang admitted TSMC’s disadvantage, its stock rose by 8%. Investors believed that Morris was very angry and there would be serious consequences. Indeed, TSMC started preparing for a multi-front counterattack.

Stand up where one falls down. So did TSMC. The company assembled an unprecedented R&D team in the industry: the Nightingale Army - a team that worked at night. TSMC learned from Foxconn assembly line and built a three-shift R&D department to ensure 24-hour uninterrupted R&D. Nightingale's salary was much higher than assembly workers or regular R&D personnel - 30% increase in base salary and 50% in dividend.

Attracted by the rewards, before long the Nightingale quickly gathered more than 400 people. Because staying up late harms the liver, the nightingale model is also called "liver buster.” A few sayings started to spread in Taiwan, “100,000 young people, 100,000 livers”, “the tougher the liver, the more money." [z]In 2014, the total annual working hours of Taiwanese laborers was 2135 hours, far exceeding the rest of the world. When Intel was defeated by TSMC’s technology in 2017, some Intel employees went to TSMC to figure out why, and the answer was: you snooze you lose [aa]; you’ve been sleeping too much for too long.

After putting in place the technical charging team, Chang turned to the lawyers and ordered them to "fight to the end". A new judge who had a Korean husband and was familiar with Korean cases replaced the old judge. TSMC’s lawyers also dug up a lot of crucial evidence, including that 10 of Liang’s students were senior engineers at Samsung; Liang started using Samsung's internal mailbox as early as 2009; 7 key features of Samsung’s process were similar to TSMC’s.

In the end, the court ruled that Liang could not return to Samsung until the end of 2015. This was the first ruling in Taiwan that even after an non-compete period ended, an former employee was still prohibited from working for a competitor. TSMC’s victory was a joint effort of Taiwanese commercial, political and legal circles. [ab] Taiwan specifically revised its Trade Secrets Act and included industrial espionage. The judge even declared publicly, “if we don’t protect companies like TSMC, who will we protect?” [ac]

Liang, of course, disagreed with the ruling and appealed to the Supreme Court of Taiwan. The lawsuit dragged on until August 2015 and Liang lost again. At this point, Liang could simply wait four months and then go back to work at Samsung, but another shock was awaiting: as Liang was tied up in the lawsuit, Samsung rushed the production and floundered on A9 chips.

Netizens found that Samsung’s foundry’s iPhone 6s chip lasted 2 hours less than TSMC’s, and the temperature rose by more than 10%. There were even tutorials online showing how to distinguish iPhones with Samsung chips so that buyers could return the product as soon as possible. Although Apple denied the performance difference, it quietly transferred the A9 order from Samsung to TSMC. On the list of foundries after A10, only TSMC was left.

TSMC once again won more than half of the OEM market share, becoming the backbone of Taiwan’s economy, stock market, and even population. TSMC's new foundry consumed a third of Taiwan's newly generated power; its 40,000 plus employees also contributed more than 1% of total newborns in Taiwan in 2019 [ad]. On average, Taiwan had one large foundry per 1,000 square kilometers, making it the leading region in foundry density globally.

In June 2018, the 86-year-old Chang announced his retirement the second time. At his last shareholder meeting, he said affectionately in applause, “TSMC's miracle will never stop!” Chang left the industry with success and achievement, while his old rival Lee Kun-hee had been ill since 2014 and until this date, hasn’t stepped out of Samsung Medical Center. Lee’s eldest son Lee Jae-yong, the de facto head of Samsung was imprisoned for bribery in 2017, and released 6 months later.

In July 2019, Japan cut off the supply of semiconductor materials to Samsung, and Lee Jae-yong had to rush to Taiwan to plead for the purchase of raw materials. This signaled the complete bankruptcy of his plan to “Kill Taiwan.” In December, TSMC's market value briefly surpassed Samsung and became the global semiconductor leader. The showdown since 2004 had gone through four stages and finally, the curtains fell.

However, just as Chang advised, what TSMC won was merely a battle. The entire semiconductor industry has been fighting since the 1970s and why won’t the war continue?

The End

TSMC becomes a totem in Taiwan, which is attributed to Chang’s personal charm, independent R&D strategy, hardworking spirit, and the principles Chang set at the beginning – staying neutral to serve, winning trust from partners.

It is based on trust that not only Apple can hand over orders without worry, but also Huawei may rest assured. All Kirin chips are all manufactured by TSMC, which contributes more than 10% of TSMC’s total orders. In this regard, Taiwanese IT Godfather Shi Zhenrong (???/Stan Shih) once said, “Taiwan is a friend of the world, while Samsung is the enemy of the world.” - meaning that Taiwan is determined to specialize and work for technology companies all over the world, while Samsung wants to expand across the sector. [ae] [af] [ag]

Of course, TSMC is still too young. When the Pacific’s tectonic plates begin to collide, mainland China and the United States are like two invisible walls. At this time, can TSMC really make friends as it pleases?

Looking back at history, four treasures at the beginning of TSMC were talents from Berkeley, management experiences from Texas Instruments, IBM's technology licensing, and orders from American chip companies. It is Apple and the United States behind it that decided the balance between Samsung and TSMC, and TSMC’s shareholders are mostly on Wall Street, holding 80% of total equity [ah] [ai].

Behind TSMC, there is always that sharp knife of Samsung. Although Samsung floundered on the 7nm process and lags behind TSMC by quite a lot, Apple and Qualcomm fear TSMC’s hegemony and will never completely discard Samsung. History of the electronics industry tells us: never underestimate the madness and guts of Koreans.

When there are high walls on both sides and a sharp knife behind the back, can TSMC maintain its commanding heights of the global chip industry? Can TSMC enjoy its neutral position as before? No one can answer that. Morris Chang can no longer come back to the battles, but his old colleagues and subordinates are standing across the strait and jumping into the torrent of history.

At the end of 2016, Chiang Shang-Yi, TSMC's No. 2, knocked on Chang’s office and told him that he would join SMIC as a director. A month later, Chiang’s entire family moved to the mainland.

Six months later, Liang Mong-Song, who resigned from Samsung, accepted an annual salary of only $200,000 and joined SMIC with his team as a co-chief executive. In only three quarters, Liang and his team brought an important 14nm technological breakthrough to SMIC.

In 2019, Yang Guanglei, who was among TSMC’s “Six R&D Gentlemen” during its defeat of IBM, took over Chiang Shang-Yi’s post as an independent board director and moved to mainland China.

Chiang’s next post is the CEO of HSMC in Wuhan. At a summit last year, he commented, "Moore's Law is slowing down. This offers an excellent opportunity to China's mainland semiconductor companies to catch and take over."

In addition to these executives, countless Taiwanese engineers rushed to the mainland and joined in writing history of the chip industry. From HiSilicon in Shenzhen to XMC in Wuhan, from JCET in Jiangyin to CXMT in Hefei, streams of engineers return from overseas, forming a turbulent wave and contributing to the last battle of China’s industries. [aj]

Therefore, TSMC is caught in between the US and China's technology war. It benefits from both sides but also faces a dilemma. It wants to be “neutral” but hard to achieve so. It is after all founded by the descendants of Yan Di and Huang Di [ak] (the Chinese people), and how can it truly be "neutral"?

[a]previous translation had this profile of Zhang Zhongmou: "At about the same time that Zhang Rujing was taken to Taiwan by his parents, 17-year-old Zhang Zhongmou, a native of Ningbo in Zhejiang, also boarded a ship in Shanghai, crammed into a narrow cabin room with his family, and set off for Hong Kong.

After staying in Hong Kong for a few months, Zhang Zhongmou immediately applied to Harvard University, becoming the only Chinese student among the school’s 1,000 or so freshmen. He later transferred to the Massachusetts Institute of Technology and obtained a master's degree. In 1958, Zhang Zhongmou joined Texas Instruments, and worked his way to the company's No. 3 position. Zhang Rujing, who joined Texas Instruments in 1977, nominally had a "colleague" relationship with Zhang Zhongmou for eight years, but contrary to the media hype, their paths did not intersect during this period.

In 1985, Zhang Zhongmou resigned from a high-paying position at Texas Instruments and returned to Taiwan to become president of the Industrial Technology Research Institute of Taiwan. Prior to this, Zhang Zhongmou, who was in his fifties, had never lived in Taiwan for a long time. In 1987, Zhang Zhongmou founded TSMC and received strong support from the government. By the time Zhang Rujing resigned from Texas Instruments and returned to Taiwan, Zhang Zhongmou had already become the industrial hero of Taiwan in the same way as Akio Morita of Japan.

"

https://docs.google.com/document/d/1g2B0YEFNkPilLB6PTGOQ0NxaO6CflWxvI4zH27h3ISw/edit?usp=sharing

Thanks for the heads up! I was translating it into Morris Chang according to TSMC press release but can change it pretty easily. One thought is maybe at the first mention of him, we can include both names since Morris is the name that's more widely reported and used in western media (forbes, qz, etc.). That way we can make sure people know who he is.

[c]Oh wow I didn't even register that the first time around translating -- yeah Morris Chang is definitely better to use actually

[d]yeah, i think Chinese folks know him as Zhongmou while American know him as Morris. There are few more names like that in this article. And it gets a bit messier when you mix in Taiwanese spelling coz it's different than pinyin.. I will highlight them all once I finish the second part translation and we can streamline them.

[e]"?????,?????"

[f]Very important

[g]endnote 2: Jensen Huang talks about Morris Chang, chairman of TSMC; a solid partner and a sincere friend -- Nvidia's Official Blog 2018

[h]A really cool anecdote

Full resolution: blogs.nvidia.com.tw

https://images.nvidia.com/content/APAC/blog/tw/jhh-mc-illustration-24x36in-r8-FOR-PRINT-FLAT-150dpi-OPT2.jpg

[j]GlobalFoundries, a key part of US DoD's Trusted Foundry Program, is an UAE-owned company

[k]Fascinating. Thank you for this context.

[l]????????

[m]very interesting

[n]another example of what I call "techlore" language

[o]And this! is very hard to translate lol

[p]https://www.nytimes.com/1987/06/12/world/a-bizarre-deal-diverts-vital-tools-to-russians.html

[q]301 Investigation also ignited US-China trade/tech war in march 2018. Very interesting.

[r]Lee Jae-yong (???)

[s]footnote 3: Declassification of Samsung's plan to destroy Taiwan - Business Today Taiwan 2013

[t]a working schedule of 9am-9pm, 6 days a week.

Endnote [4]:

??COO:???iPhone???????????? - ????

Apple COO: Giving Apple Chip Order to TSMC Was A Gamble - Sino Technology.

http://tech.sina.com.cn/it/2017-10-23/doc-ifymzzpw0009075.shtml

[v]how much an industry champion means for entire Taiwan.

[w]Should this be "Beyond Moore" (i.e., Moore's Law)?

[x]Yep great catch -- thanks!

[y]Endnote 7:

?????? ????????-???? 2011

TSMC Former Director Liang Mong-Song Complained in Tears of Being Pushed Out - Business Times

[z]more techlore -- this is written in like a heroic epic poem style

[aa]I can't help myself... lolll

[ab]thought provoking.

[ac]Endnote 5:

????-??????????? -???? 2015

Hunting Rebel - Demystifying Liang Mong-Song's Exertion in Samsung - Tianxia Magazine 2015.

[ad]Endnote 6:

2018?????????????

2018 TSMC Corporate Social Responsibility Report

[ae]very interesting.

[af]Very interesting perception of Samsung's business model. Question: How does that fit to Samsung's plans to ramp up their contract foundry business? taipeitimes.com

[ag]i wonder if this is more of a "we also want to do foundry business" or "we are going to *exclusively* focus on foundry business." as long as samsung spans across the entire supply chain (aka making both chips and phones), the collaborative-competitive dynamic persists.

[ah]This paragraph is confusingly worded. What is the connection between Apple deciding it and TSMC shareholders?

[ai]I changed the "Whereas" to "and" -- I think the connection is just that there's a lot of American capital behind TSMC -- whether it's human capital, investments, chip orders, etc.

[aj]the last block of the industrialization pyramid.

[ak]???? -- Yan Di and Huang Di were two legendary rulers of remote antiquity

[InternetJustice] Graphene won't be towards an end of Moore's law, neither will Carbon Nanotubing....

InternetJustice — 3/4/2021 9:21:34 AM

Graphene won't be towards an end of Moore's law, neither will Carbon Nanotubing. It will be a step closer though.

[FJB] Graphene 'Nano-Origami' Could Take Us Past the End of Moore's Law ...

FJB — 3/3/2021 9:42:23 AM

Graphene 'Nano-Origami' Could Take Us Past the End of Moore's Law
Edd Gent

singularityhub.com

Wonder material graphene is often touted as a potential way around the death of Moore’s Law, but harnessing its promising properties has proven tricky. Now, researchers have shown they can build graphene chips 100 times smaller than normal ones using a process they’ve dubbed “nano-origami.”

For decades our ability to miniaturize electronic components improved exponentially, and with it the performance of our chips. But in recent years we’ve started approaching the physical limits of the silicon technology we’ve become so reliant on, and progress is slowing.

The ability to build ever-faster chips has underpinned the rapid technological advances we’ve made in the last half-century, so understandably people are keen to keep that trend going. As a result, a plethora of new technologies are vying to take us past the end of Moore’s Law, but so far none have taken an obvious lead.

One of the most promising candidates is graphene, a form of carbon that comes in one-atom-thick sheets, which are both incredibly strong and have a range of remarkable electronic properties. Despite its potential, efforts to create electronics out of graphene and similar 2D materials have been progressing slowly.

One of the reasons is that the processes used to create these incredibly thin layers inevitably introduce defects that can change the properties of the material. Typically, these imperfections are seen as problematic, as any components made this way may not behave as expected.

But in a paper published in the journal ACS Nano, researchers from the University of Sussex in the UK decided to investigate exactly how these defects impact the properties of graphene and another 2D material called molybdenum disulfide, and how they could be exploited to design ultra-small microchips.

Building on their findings, the team has now shown that they can direct these defects to create minuscule electronic components. By wrinkling a sheet of graphene, they were able to get it to behave like a transistor without adding any additional materials.

“We’re mechanically creating kinks in a layer of graphene. It’s a bit like nano-origami,” Alan Dalton, who led the research, said in a press release.

“Using these nanomaterials will make our computer chips smaller and faster. It is absolutely critical that this happens as computer manufacturers are now at the limit of what they can do with traditional semiconducting technology.”

The work falls into an emerging line of research known as “straintronics,” which is uncovering the surprising ways in which mechanical strains in nanomaterials can dramatically change their electronic, magnetic, and even optical characteristics.

Now that the researchers have elucidated how different kinds of defects like wrinkles, domes, and holes impact the properties of these 2D materials, they’re working on ways to precisely pattern them to create more complex chips.

According to New Scientist, they have already mastered creating rows of wrinkles using pattern molds and generating domes by firing lasers at water molecules to make them expand, and they hope to have a functional prototype chip within five years.

They say that the approach allows them to build processors around 100 times smaller than conventional microchips, which could be thousands of times faster than today’s devices and would require far less energy and resources to make.

There’s still a long way to go to flesh out the potential of the approach, but it represents a promising new front in the race to keep the technological juggernaut we’ve created steaming ahead at full power.

Image Credit: seagul from Pixabay

[FJB] Imec demonstrates 20-nm pitch line/space resist imaging with high-NA EUV interfe...

FJB — 2/24/2021 8:09:46 PM

Imec demonstrates 20-nm pitch line/space resist imaging with high-NA EUV interference lithography
Science X staff
techxplore.com /news/2021-02-imec-nm-pitch-linespace-resist.html

Schematic representations (not to scale) of Lloyd’s Mirror setup for high-NA EUV interference coupon experiments . Credit: IMEC
Imec reports for the first time the use of a 13.5-nm, high-harmonic-generation source for the printing of 20-nm pitch line/spaces using interference lithographic imaging of an Inpria metal-oxide resist under high-numerical-aperture (high-NA) conditions. The demonstrated high-NA capability of the EUV interference lithography using this EUV source presents an important milestone of the AttoLab, a research facility initiated by imec and KMLabs to accelerate the development of the high-NA patterning ecosystem on 300 mm wafers. The interference tool will be used to explore the fundamental dynamics of photoresist imaging and provide patterned 300 mm wafers for process development before the first 0.55 high-NA EXE5000 prototype from ASML becomes available.

The high-NA exposure at 13.5 nm was emulated with a coherent high-flux laser source of KMLabs in a Lloyd's-Mirror-based interference setup for coupon experiments on imec's spectroscopy beamline. This apparatus supplies critical learning for the next step, expansion to 300 mm wafer interference exposures. In this arrangement, light reflected from a mirror interferes with light directly emitted by the 13.5 nm laser source, generating a finely detailed interference pattern suited for resist imaging. The pitch of the imaged resist pattern can be tuned by changing the angle between the interfering light beams. With this setup, 20 nm line/spaces could for the first time at imec be successfully patterned in an Inpria metal-oxide resist (exposure dose range of ~54-64mJ/cm2, interference angle 20 degrees) using a single-exposure, coated on coupon samples.

"The high-flux laser source of KMLabs was used at a record small wavelength of 13.5 nm, emitting a series of attosecond (10-18s) pulses that reaches the photoresist with a pulse duration that is a few femtoseconds (10-15s) in width. This imposed challenging requirements on the temporal coherence of the interfering waves," explains John Petersen, Principal Scientist at imec and SPIE Fellow. "The demonstrated capability of this setup for emulating high-NA EUV lithography exposures is an important AttoLab milestone. It demonstrates that we can synchronize femtosecond wide pulses, that we have excellent vibration control, and excellent beam pointing stability. The 13.5 nm femtosecond enveloped attosecond laser pulses allow us to study EUV photon absorption and ultrafast radiative processes that are subsequently induced in the photoresist material. For these studies, we will couple the beamline with spectroscopy techniques, such as time-resolved infrared and photoelectron spectroscopy, that we earlier installed within the laboratory facility. The fundamental learnings from this spectroscopy beamline will contribute to developing the lithographic materials required for the next-generation (i.e., 0.55 NA) EUV lithography scanners, before the first 0.55 EXE5000 proto-type becomes available."

Interference chamber for full-wafer experiments. Credit: IMEC
Next up, the learnings from this first proof of concept will now be transferred to a second, 300mm-wafer-compatible EUV interference lithography beamline that is currently under installation. This beamline is designed for screening various resist materials under high-NA conditions with a few seconds per single-exposure, and for supporting the development of optimized pattern, etch and metrology technologies viable for high-NA EUV lithography."The lab's capabilities are instrumental for fundamental investigations to accelerate material development toward high NA EUV," said Andrew Grenville, CEO of Inpria. "We are looking forward to deeper collaboration with the AttoLab."

(Left) Cross-section SEM image of a 20nm L/S pattern imaged an Inpria metal-oxide resist, exposed in a Lloyd’s mirror interference setup at a dose of 64mJ/cm2 and interference angle 20°. (Right) Fourier transform analysis where 0.05=20nm pitch. Credit: IMEC
"Our interference tools are designed to go from 32 nm pitch to an unprecedented 8 nm pitch on 300 mm wafers, as well as smaller coupons," says John Petersen. "They will offer complementary insights in what is already gained from 0.33NA EUV lithography scanners—which are currently being pushed to their ultimate single-exposure resolution limits. In addition to patterning, many other materials research areas will benefit from this state-of-the-art AttoLab research facility. For example, the ultrafast analytic capability will accelerate materials development of the next-generation logic, memory, and quantum devices, and of the next-generation metrology and inspection techniques."

More information: Introduction to imec's AttoLab for ultrafast kinetics of EUV exposure processes and ultra-small pitch lithography, Paper 11610-46

Citation: Imec demonstrates 20-nm pitch line/space resist imaging with high-NA EUV interference lithography (2021, February 23) retrieved 24 February 2021 from techxplore.com

This document is subject to copyright. Apart from any fair dealing for the purpose of private study or research, no part may be reproduced without the written permission. The content is provided for information purposes only.

[sense] That one was pretty exciting.... Right up to the point where, first, it mention...

sense — 2/17/2021 9:01:12 PM

That one was pretty exciting....

Right up to the point where, first, it mentions being made of Strotiummm and Rhodiummm... and then the bit about achieving "almost" unity...

How "almost" is it ?

Others might well have an ability to tweak some aspects to get "almost" close enough to over the hump to offer an economic reason to get it out of the lab ?

Thanks for providing the brain floss.

[sense] Hmmm. The new future... just like the old future ? At least, after decades of ...

sense — 2/17/2021 8:14:12 PM

Hmmm. The new future... just like the old future ?

At least, after decades of hearing about how germanium was going to replace silicon in the next generation, and then, the next, ad infinitum....

There seems to be a broad consensus now that germanium transistors are definitively better... in fuzz pedals.

Otherwise <crickets chirping>.

The incremental improvements delivered to us by the academic-corporate research-industrial standards coordinating complex... do seem to ensure you can earn a degree in a related engineering field and have it not be made obsolete for an entire career... /s

[J_F_Shepard] To: J_F_Shepard who wrote (649) 2/10/2021 6:21:31 PM From: FUBHO of 971 DEM...

J_F_Shepard — 2/10/2021 6:23:55 PM

To: J_F_Shepard who wrote (649)	2/10/2021 6:21:31 PM
From: FUBHO	of 971

DEMORATS LEAVING PARTY THANKS TO HATEFUL RHETORIC OF DEMENTIA, AOC, PELOSI, MAXINE... WRIGHT: I’m A Democrat, But It’s Time To Leave The Party

[FJB] Photocatalyst that can Split Water into Hydrogen and oxygen at a Quant...

FJB — 12/26/2020 7:30:12 AM

Photocatalyst that can Split Water into Hydrogen and oxygen at a Quantum Efficiency Close to 100% - FuelCellsWorks
By FuelCellsWorks

fuelcellsworks.com

A research team led by Shinshu University’s Tsuyoshi Takata, Takashi Hisatomi and Kazunari Domen succeeded in developing a photocatalyst that can split water into hydrogen and oxygen at a quantum efficiency close to 100%.

The team consisted of their colleagues from Yamaguchi University, The University of Tokyo and National Institute of Advanced Industrial Science and Technology (AIST).

The team produced an ideal photocatalyst structure composed of semiconductor particles and cocatalysts. H2 and O2 evolution cocatalysts were selectively photodeposited on different facets of crystalline SrTiO3(Al-doped) particles due to anisotropic charge transport. This photocatalyst structure effectively prevented charge recombination losses, reaching the upper limit of quantum efficiency.

Figure 1 – Schematic structure (a) and scanning electron microscope image (b) of Al-doped SrTiO3 site-selectively coloaded with a hydrogen evolution cocatalyst (Rh/Cr2O3) and an oxygen evolution cocatalyst (CoOOH).

Water splitting reaction driven by solar energy is a technology for producing renewable solar hydrogen on a large scale. To put such technology to practical use, the production cost of solar hydrogen must be significantly reduced [1]. This requires the reaction system that can split water efficiently and can be scaled up easily. A system consisting of particulate semiconductor photocatalysts can be expanded over a large area with relatively simple processes. Therefore, it will make great strides toward large-scale solar hydrogen production if photocatalysts driving the sunlight-driven water splitting reaction with high efficiency are developed.

To upgrade the solar energy conversion efficiency of photocatalytic water splitting, it is necessary to improve two factors: widening the wavelength range of light used by the photocatalyst for the reaction and increasing the quantum yield at each wavelength. The former is determined by the bandgap of the photocatalyst material used, and the latter is determined by the quality of the photocatalyst material and the functionality of the cocatalyst used to promote the reaction. However, photocatalytic water splitting is an endergonic reaction involving multi-electron transfer occurring in a non-equilibrium state.

This study refined the design and operating principle for advancing water splitting methods with a high quantum efficiency. The knowledge obtained in this study will propel the field of photocatalytic water splitting further to enable the scalable solar hydrogen production.

The project was made possible through the support of NEDO (New Energy and Industrial Technology Development Organization) under the “Artificial photosynthesis project”.

Title: Photocatalytic water splitting with a quantum efficiency of almost unity
Authors:Tsuyoshi Takata, Junzhe Jiang, Yoshihisa Sakata, Mamiko Nakabayashi, Naoya Shibata, Vikas Nandal, Kazuhiko Seki, Takashi Hisatomi, Kazunari Domen
Journal:Nature, 581, 411-414 (2020)
DOI10.1038/s41586-020-2278-9

[FJB] Fermilab and partners achieve sustained, high-fidelity quantum teleportati...

FJB — 12/25/2020 10:08:54 PM

Fermilab and partners achieve sustained, high-fidelity quantum teleportation

December 15, 2020

news.fnal.gov

Media contact

Leah Hesla, Fermilab, media@fnal.gov, 630-840-3351

A viable quantum internet — a network in which information stored in qubits is shared over long distances through entanglement — would transform the fields of data storage, precision sensing and computing, ushering in a new era of communication.

This month, scientists at Fermilab, a U.S. Department of Energy Office of Science national laboratory, and their partners took a significant step in the direction of realizing a quantum internet.

In a paper published in PRX Quantum, the team presents for the first time a demonstration of a sustained, long-distance (44 kilometers of fiber) teleportation of qubits of photons (quanta of light) with fidelity greater than 90%. The qubits were teleported over a fiber-optic network using state-of-the-art single-photon detectors and off-the-shelf equipment.

“We’re thrilled by these results,” said Fermilab scientist Panagiotis Spentzouris, head of the Fermilab quantum science program and one of the paper’s co-authors. “This is a key achievement on the way to building a technology that will redefine how we conduct global communication.”

In a demonstration of high-fidelity quantum teleportation at the Fermilab Quantum Network, fiber-optic cables connect off-the-shelf devices (shown above), as well as state-of-the-art R&D devices. Photo: Fermilab

Quantum teleportation is a “disembodied” transfer of quantum states from one location to another. The quantum teleportation of a qubit is achieved using quantum entanglement, in which two or more particles are inextricably linked to each other. If an entangled pair of particles is shared between two separate locations, no matter the distance between them, the encoded information is teleported.

The joint team — researchers at Fermilab, AT&T, Caltech, Harvard University, NASA Jet Propulsion Laboratory and University of Calgary — successfully teleported qubits on two systems: the Caltech Quantum Network, or CQNET, and the Fermilab Quantum Network, or FQNET. The systems were designed, built, commissioned and deployed by Caltech’s public-private research program on Intelligent Quantum Networks and Technologies, or IN-Q-NET.

“We are very proud to have achieved this milestone on sustainable, high-performing and scalable quantum teleportation systems,” said Maria Spiropulu, Shang-Yi Ch’en professor of physics at Caltech and director of the IN-Q-NET research program. “The results will be further improved with system upgrades we are expecting to complete by Q2 2021.”

CQNET and FQNET, which feature near-autonomous data processing, are compatible both with existing telecommunication infrastructure and with emerging quantum processing and storage devices. Researchers are using them to improve the fidelity and rate of entanglement distribution, with an emphasis on complex quantum communication protocols and fundamental science.

The achievement comes just a few months after the U.S. Department of Energy unveiled its blueprint for a national quantum internet at a press conference in Chicago.

“With this demonstration we’re beginning to lay the foundation for the construction of a Chicago-area metropolitan quantum network,” Spentzouris said. The Chicagoland network, called the Illinois Express Quantum Network, is being designed by Fermilab in collaboration with Argonne National Laboratory, Caltech, Northwestern University and industry partners.

This research was supported by DOE’s Office of Science through the Quantum Information Science-Enabled Discovery (QuantISED) program.

“The feat is a testament to success of collaboration across disciplines and institutions, which drives so much of what we accomplish in science,” said Fermilab Deputy Director of Research Joe Lykken. “I commend the IN-Q-NET team and our partners in academia and industry on this first-of-its-kind achievement in quantum teleportation.”

Learn more about the result.

Fermilab is America’s premier national laboratory for particle physics and accelerator research. A U.S. Department of Energy Office of Science laboratory, Fermilab is located near Chicago, Illinois, and operated under contract by the Fermi Research Alliance LLC, a joint partnership between the University of Chicago and the Universities Research Association, Inc. Visit Fermilab’s website at www.fnal.gov and follow us on Twitter at @Fermilab.

The Office of Science is the single largest supporter of basic research in the physical sciences in the United States and is working to address some of the most pressing challenges of our time. For more information, visit science.energy.gov.

Tagged: California, Caltech, IN-Q-NET, quantum communication, quantum information science, quantum science, quantum teleportation

[FJB] The Future of Computation: AI, ARM, and RISC-V | CogX 2020 [youtube video]

FJB — 12/20/2020 4:55:33 PM

[FJB] Aging Problems At 5nm And Below semiengineering.com ...

FJB — 6/15/2020 6:09:28 AM

Aging Problems At 5nm And Below

semiengineering.com

The mechanisms that cause aging in semiconductors have been known for a long time, but the concept did not concern most people because the expected lifetime of parts was far longer than their intended deployment in the field. In a short period of time, all of that has changed.

As device geometries have become smaller, the issue has become more significant. At 5nm, it becomes an essential part of the development flow with tools and flows evolving rapidly as new problems are discovered, understood and modeled.

“We have seen it move from being a boutique technology, used by specific design groups, into something that’s much more of a regular part of the sign-off process,” says Art Schaldenbrand, senior product manager at Cadence. “As we go down into these more advanced nodes, the number of issues you have to deal with increases. At half micron you might only have to worry about hot carrier injection (HCI) if you’re doing something like a power chip. As you go down below 180nm you start seeing things like negative-bias temperature instability (NBTI). Further down you get into other phenomena like self heating, which becomes a significant reliability problem.”

The ways of dealing with it in the past are no longer viable. “Until recently, designers very conservatively dealt with the aging problem by overdesign, leaving plenty of margin on the table,” says Ahmed Ramadan, senior product engineering manager for Mentor, a Siemens Business. “However, while pushing designs to the limit is not only needed to achieve competitive advantage, it is also needed to fulfill new applications requirements given the diminishing transistor scaling benefits. All of these call for the necessity of accurate aging analysis.”

While new phenomena are being discovered, the old ones continue to get worse. “The drivers of aging, such as temperature and electrical stress, have not really changed,” says André Lange, group manager for quality and reliability at Fraunhofer IIS’ Engineering of Adaptive Systems Division. “However, densely packed active devices with minimum safety margins are required to realize advanced functionality requirements. This makes them more susceptible to reliability issues caused by self-heating and increasing field strengths. Considering advanced packaging techniques with 2.5D and 3D integration, the drivers for reliability issues, especially temperature, will gain importance.”

Contributing factors
The biggest factor is heat. “Higher speeds tends to produce higher temperatures and temperature is the biggest killer,” says Rita Horner, senior product marketing manager for 3D-IC at Synopsys. “Temperature exacerbates electron migration. The expected life can exponentially change from a tiny delta in temperature.”

This became a much bigger concern with finFETs. “In a planar CMOS process, heat can escape through the bulk of the device into the substrate fairly easily,” says Cadence’s Schaldenbrand. “But when you stand the transistor on its side and wrap it in a blanket, which is effectively what the gate oxide and gate acts like, the channel experiences greater temperature rise, so the stress that a device is experiencing increases significantly.”

An increasing amount of electronics are finding themselves being deployed in hostile environments. “Semiconductor chips that operate in extreme conditions, such as automotive (150° C) or high elevation (data servers in Mexico City) have the highest risk of reliability and aging related constraints,” says Milind Weling, senior vice president of programs and operations at Intermolecular. “ 2.5D and 3D designs could see additional mechanical stress on the underlying silicon chips, and this could induce additional mechanical stress aging.”

Devices’ attributes get progressively worse. “Over time, the threshold voltage of a device degrades, which means that it takes more time to turn the device on,” says Haran Thanikasalam, senior applications engineer for AMS at Synopsys. “One reason for this is negative bias instability. But as devices scale down, voltage scaling has been slower than geometry scaling. Today, we are reaching the limits of physics. Devices are operating somewhere around 0.6 to 0.7 volts at 3nm, compared to 1.2V at 40nm or 28nm. Because of this, the electric fields have increased. Large electrical field over a very tiny device area can cause severe breakdown.”

This is new. “The way we capture this phenomenon is something called time-dependent dielectric breakdown (TTDB),” says Schaldenbrand. “You’re looking at how that field density causes devices to break down, and making sure the devices are not experiencing too much field density.”

The other primary cause of aging is electromigration (EM). “If you perform reliability simulation, like EM or IR drop simulation, not only do the devices degrade but you also have electromigration happening on the interconnects,” adds Thanikasalam. “You have to consider not only the devices, but also the interconnects between the devices.”

Analog and digital
When it comes to aging, digital is a subset of analog. “In digital, you’re most worried about drive, because that changes the rise and fall delays,” says Schaldenbrand. “That covers a variety of sins. But analog is a lot more subtle and gain is something you worry about. Just knowing that Vt changed by this much isn’t going to tell you how much your gain will degrade. That’s only one part of the equation.”

Fig 1: Failure of analog components over time. Source: Synopsys

Aging can be masked in digital. “Depending on the application, a system may just degrade, or it may fail from the same amount of aging,” says Mentor’s Ramadan. “For example, microprocessor degradation may lead to lower performance, necessitating a slowdown, but not necessary failures. In mission-critical AI applications, such as ADAS, a sensor degradation may directly lead to AI failures and hence system failure.”

That simpler notion of degradation for digital often can be hidden. “A lot of this is captured at the cell characterization level,” adds Schaldenbrand. “So the system designer doesn’t worry about it much. If he runs the right libraries, the problem is covered for him.”

Duty cycle
In order to get an accurate picture for aging, you have to consider activity in the design, but often this is not in the expected manner. “Negative bias temperatures stability (NBTS) is affecting some devices,” says Synopsys’ Horner. “But the devices do not have to be actively running. Aging can be happening while the device is shut off.”

In the past the analysis was done without simulation. “You can only get a certain amount of reliability data from doing static, vector independent analysis,” says Synopsys’ Thanikasalam. “This analysis does not care about the stimuli you give to your system. It takes a broader look and identifies where the problems are happening without simulating the design. But that is proving to be a very inaccurate way of doing things, especially at smaller nodes, because everything is activity-dependent.”

That can be troublesome for IP blocks. “The problem is that if somebody is doing their own chip, their own software in their own device, they have all the information they need to know, down to the transistor level, what that duty cycle is,” says Kurt Shuler, vice president of marketing at Arteris IP. “But if you are creating a chip that other people will create software for, or if you’re providing a whole SDK and they’re modifying it, then you don’t really know. Those chip vendors have to provide to their customers some means to do that analysis.”

For some parts of the design, duty cycles can be estimated. “You never want to find a block level problem at the system level,” says Schaldenbrand. “People can do the analysis at the block level, and it’s fairly inexpensive to do there. For an analog block, such as an ADC or a SerDes or a PLL, you have a good idea of what its operation is going to be within the system. You know what kind of stresses it will experience. That is not true for a large digital design, where you might have several operating modes. That will change digital activity a lot.”

This is the fundamental reason why it has turned into a user issue. “It puts the onus on the user to make sure that you pick stimulus that will activate the parts of the design that you think are going to be more vulnerable to aging and electromigration, and you have to do that yourself,” says Thanikasalam. “This has created a big warning sign among the end users because the foundries won’t be able to provide you with stimulus. They have no clue what your design does.”

Monitoring and testing
The industry approaches are changing at multiple levels. “To properly assess aging in a chip, manufacturers have relied on a function called burn-in testing, where the wafer is cooked to artificially age it, after which it can be tested for reliability,” says Syed Alam, global semiconductor lead for Accenture. “Heat is the primary factor for aging in chips, with usage a close second, especially for flash as there are only so many re-writes available on a drive.”

And this is still a technique that many rely on. “AEC-Q100, an important standard for automotive electronics, contains multiple tests that do not reveal true reliability information,” says Fraunhofer’s Lange. “For example, in high-temperature operating life (HTOL) testing, 3×77 devices have to be stressed for 100 hours with functional tests before and after stress. Even when all devices pass, you cannot tell whether they will fail after 101 hours or whether they will last 10X longer. This information can only be obtained by extended testing or simulations.”

An emerging alternative is to build aging sensors into the chip. “There are sensors, which usually contain a timing loop, and they will warn you when it takes longer for the electrons to go around a loop,” says Arteris IP’s Shuler. “There is also a concept called canary cells, where these are meant to die prematurely compared to a standard transistor. This can tell you that aging is impacting the chip. What you are trying to do is to get predictive information that the chip is going to die. In some cases, they are taking the information from those sensors, getting that off chip, throwing it into big database and running AI algorithms to try to do predictive work.”

Additional 3D issues
Many of the same problems exist in 2D, 2.5D and 3D designs, except that thermal issues may become more amplified with some architectures. But there also may be a whole bunch of new issues that are not yet fully understood. “When you’re stacking devices on top of each other, you have to back-grind them to thin them,” says Horner. “The stresses on the thinner die could be a concern, and that needs to be understood and studied and addressed in terms of the analysis. In addition, various types of the silicon age differently. You’re talking about a heterogeneous environment where you are potentially stacking DRAM, which tends to be more of a specific technology — or CPUs and GPUs, which may utilize different technology process nodes. You may have different types of TSVs or bumps that have been used in this particular silicon. How do they interact with each other?”

Those interfaces are a concern. “There is stress on the die, and that changes the device characteristics,” says Schaldenbrand. “But if different dies heat up to different temperatures, then the places where they interface are going to have a lot of mechanical stress. That’s a big problem, and system interconnect is going to be a big challenge going forward.”

Models and analysis
It all starts with the foundries. “The TSMCs and the Samsungs of the world have to start providing that information,” says Shuler. “As you get to 5nm and below, even 7nm, there is a lot of variability in these processes and that makes everything worse.”

“The foundries worried about this because they realized that the devices being subjected to higher electric fields were degrading much faster than before,” says Thanikasalam. “They started using the MOS reliability and analysis solution (MOSRA) that applies to the device aging part of it. Recently, we see that shift towards the end customers who are starting to use the aging models. Some customers will only do a simple run using degraded models so that the simulation accounts for the degradation of the threshold voltage.”

High-volume chips will need much more extensive analysis. “For high-volume production, multi PVT simulations are becoming a useless way of verifying this,” adds Thanikasalam. Everybody has to run Monte Carlo at this level. Monte Carlo simulation with the variation models is the key in 5nm and below.”

More models are needed. “There are more models being created and optimized,” says Horner. “In terms of 3D stacking, we have knowledge of the concern about electromigration, IR, thermal, and power. Those are the key things that are understood and modeled. For the mechanical aspects — even the materials that we put between the layers and their effect in terms of heat, and also the stability structures — while there are models out there, they are not as enhanced because we haven’t seen enough of these yet.”

Schaldenbrand agrees. “We are constantly working on the models and updating them, adding new phenomena as people become aware of them. There’s been a lot of changes required to get ready for the advanced nodes. For the nominal device we can very well described aging, but the interaction between process variation and its effect on reliability is something that’s still a research topic. That is a very challenging subject.”

With finFETs, the entire methodology changed. “The rules have become so complicated that you need to have a tool that can actually interpret the rules, apply the rules, and tell us where there could be problems two, three years down the line,” says Thanikasalam. “FinFETs can be multi threshold devices, so when you have the entire gamut of threshold voltage being used in a single IP, we have so many problems because every single device will go in different direction.”

Conclusion
Still, progress is being made. “Recently, we have seen many foundries, IDMs, fabless and IP companies rushing to find a solution,” says Ramadan. “They cover a wide range of applications and technology processes. Whereas a standard aging model can be helpful as a starting point for new players, further customizations are expected depending on the target application and the technology process. The Compact Modeling Coalition (CMC), under the Silicon Integration Initiative (Si2), currently is working on developing a standard aging model to help the industry. In 2018, the CMC released the first standard Open Model Interface (OMI) that enables aging simulation for different circuit simulators using the unified standard OMI interface.”

That’s an important piece, but there is still a long road ahead. “Standardization activities within the CMC have started to solve some of these issues,” says Lange. “But there is quite a lot of work ahead in terms of model complexity, characterization effort, application scenario, and tool support.”

Related Stories
Circuit Aging Becoming A Critical Consideration
As reliability demands soar in automotive and other safety-related markets, tools vendors are focusing on an area often ignored in the past.
How Chips Age
Are current methodologies sufficient for ensuring that chips will function as expected throughout their expected lifetimes?
Different Ways To Improve Chip Reliability
Push toward zero defects requires more and different kinds of test in new places.
Taming NBTI To Improve Device Reliability
Negative-bias temperature instability can cause an array of problems at advanced nodes and reduced voltages.

[trickydick] FUBHO: Fascinating material, of which I probably understood about 1%, if I'm lu...

trickydick — 4/22/2020 3:57:35 PM

FUBHO: Fascinating material, of which I probably understood about 1%, if I'm lucky. BUT, what's this have to do with IMMU and it's stock activity? Do you understand this material? If you do, can you give us a very short summary of what this means? The only question I can think of is: Is this theorem work associated with sub atomic physics? Just curious, thank you.

[FJB] ‘Amazing’ Math Bridge Extended Beyond Fermat’s Last Theorem By Eri...

FJB — 4/8/2020 11:16:53 AM

‘Amazing’ Math Bridge Extended Beyond Fermat’s Last Theorem
By Erica Klarreich

April 6, 2020

quantamagazine.org

Robert Langlands, who conjectured the influential Langlands correspondence about 50 years ago, giving a talk at the Institute for Advanced Study in Princeton, New Jersey, in 2016.

Dan Komoda/Institute for Advanced Study

Namely, for both Diophantine equations and automorphic forms, there’s a natural way to generate an infinite sequence of numbers. For a Diophantine equation, you can count how many solutions the equation has in each clock-style arithmetic system (for example, in the usual 12-hour clock, 10 + 4 = 2). And for the kind of automorphic form that appears in the Langlands correspondence, you can compute an infinite list of numbers analogous to quantum energy levels.

If you include only the clock arithmetics that have a prime number of hours, Langlands conjectured that these two number sequences match up in an astonishingly broad array of circumstances. In other words, given an automorphic form, its energy levels govern the clock sequence of some Diophantine equation, and vice versa.

This connection is “weirder than telepathy,” Emerton said. “How these two sides communicate with each other … for me it seems incredible and amazing, even though I have been studying it for over 20 years.”

In the 1950s and 1960s, mathematicians figured out the beginnings of this bridge in one direction: how to go from certain automorphic forms to elliptic curves with coefficients that are rational numbers (ratios of whole numbers). Then in the 1990s, Wiles, with contributions from Taylor, figured out the opposite direction for a certain family of elliptic curves. Their result gave an instant proof of Fermat’s Last Theorem, since mathematicians had already shown that if Fermat’s Last Theorem were false, at least one of those elliptic curves would not have a matching automorphic form.

Fermat’s Last Theorem was far from the only discovery to emerge from the construction of this bridge. Mathematicians have used it, for instance, to prove the Sato-Tate conjecture, a decades-old problem about the statistical distribution of the number of clock solutions to an elliptic curve, as well as a conjecture about the energy levels of automorphic forms that originated with the legendary early 20th-century mathematician Srinivasa Ramanujan.

After Wiles and Taylor published their findings, it became clear that their method still had some juice. Soon mathematicians figured out how to extend the method to all elliptic curves with rational coefficients. More recently, mathematicians figured out how to cover coefficients that include simple irrational numbers, such as 3 + $latex \sqrt{2}$.

What they couldn’t do, however, was extend the Taylor-Wiles method to elliptic curves whose coefficients include complex numbers such as i (the square root of -1) or 3 + i or $latex \sqrt{2}$i. Nor could they handle Diophantine equations with exponents much higher than those in elliptic curves. Equations where the highest exponent on the right-hand side is 4 instead of 3 come along for free with the Taylor-Wiles method, but as soon as the exponent rises to 5, the method no longer works.

Mathematicians gradually realized that for these two next natural extensions of the Langlands bridge, it wasn’t simply a matter of finding some small adjustment to the Taylor-Wiles method. Instead, there seemed to be a fundamental obstruction.

They’re “the next examples you’d think of,” Gee said. “But you’re told, ‘No, these things are hopelessly out of reach.’”

The problem was that the Taylor-Wiles method finds the matching automorphic form for a Diophantine equation by successively approximating it with other automorphic forms. But in the situations where the equation’s coefficients include complex numbers or the exponent is 5 or higher, automorphic forms become exceedingly rare — so rare that a given automorphic form will usually have no nearby automorphic forms to use for approximation purposes.

In Wiles’ setting, the automorphic form you’re seeking “is like a needle in a haystack, but the haystack exists,” Emerton said. “And it’s almost as if it’s like a haystack of iron filings, and you’re putting in this magnet so it lines them up to point to your needle.”

But when it comes to complex-number coefficients or higher exponents, he said, “it’s like a needle in a vacuum.”

Going to the Moon Many of today’s number theorists came of age in the era of Wiles’ proof. “It was the only piece of mathematics I ever saw on the front page of a newspaper,” recalled Gee, who was 13 at the time. “For many people, it’s something that seemed exciting, that they wanted to understand, and then they ended up working in this area because of that.”

So when in 2012, two mathematicians — Frank Calegari of the University of Chicago and David Geraghty (now a research scientist at Facebook) — proposed a way to overcome the obstruction to extending the Taylor-Wiles method, their idea sent ripples of excitement through the new generation of number theorists.

Their work showed that “this fundamental obstruction to going any further is not really an obstruction at all,” Gee said. Instead, he said, the seeming limitations of the Taylor-Wiles method are telling you “that in fact you’ve only got the shadow of the actual, more general method that [Calegari and Geraghty] introduced.”

In the cases where the obstruction crops up, the automorphic forms live on higher-dimensional tilings than the two-dimensional Escher-style tilings Wiles studied. In these higher-dimensional worlds, automorphic forms are inconveniently rare. But on the plus side, higher-dimensional tilings often have a much richer structure than two-dimensional tilings do. Calegari and Geraghty’s insight was to tap into this rich structure to make up for the shortage of automorphic forms.

More specifically, whenever you have an automorphic form, you can use its “coloring” of the tiling as a sort of measuring tool that can calculate the average color on any chunk of the tiling you choose. In the two-dimensional setting, automorphic forms are essentially the only such measuring tools available. But for higher-dimensional tilings, new measuring tools crop up called torsion classes, which assign to each chunk of the tiling not an average color but a number from a clock arithmetic. There’s an abundance of these torsion classes.

For some Diophantine equations, Calegari and Geraghty proposed, it might be possible to find the matching automorphic form by approximating it not with other automorphic forms but with torsion classes. “The insight they had was fantastic,” Caraiani said.

Calegari and Geraghty provided the blueprint for a much broader bridge from Diophantine equations to automorphic forms than the one Wiles and Taylor built. Yet their idea was far from a complete bridge. For it to work, mathematicians would first have to prove three major conjectures. It was, Calegari said, as if his paper with Geraghty explained how you could get to the moon — provided someone would obligingly whip up a spaceship, rocket fuel and spacesuits. The three conjectures “were completely beyond us,” Calegari said.

In particular, Calegari and Geraghty’s method required that there already be a bridge going in the other direction, from automorphic forms to the Diophantine equations side. And that bridge would have to transport not just automorphic forms but also torsion classes. “I think a lot of people thought this was a hopeless problem when Calegari and Geraghty first outlined their program,” said Taylor, who is now at Stanford University.

Yet less than a year after Calegari and Geraghty posted their paper online, Peter Scholze — a mathematician at the University of Bonn who went on to win the Fields Medal, mathematics’ highest honor — astonished number theorists by figuring out how to go from torsion classes to the Diophantine equations side in the case of elliptic curves whose coefficients are simple complex numbers such as 3 + 2i or 4 - $latex \sqrt{5}$i. “He’s done a lot of exciting things, but that’s perhaps his most exciting achievement,” Taylor said.

Scholze had proved the first of Calegari and Geraghty’s three conjectures. And a pair of subsequent papers by Scholze and Caraiani came close to proving the second conjecture, which involves showing that Scholze’s bridge has the right properties.

It started to feel as if the program was within reach, so in the fall of 2016, to try to make further progress, Caraiani and Taylor organized what Calegari called a “secret” workshop at the Institute for Advanced Study. “We took over the lecture room — no one else was allowed in,” Calegari said.

After a couple of days of expository talks, the workshop participants started realizing how to both polish off the second conjecture and sidestep the third conjecture. “Maybe within a day of having actually stated all the problems, they were all solved,” said Gee, another participant.

The participants spent the rest of the week elaborating various aspects of the proof, and over the next two years they wrote up their findings into a 10-author paper — an almost unheard-of number of authors for a number theory paper. Their paper essentially establishes the Langlands bridge for elliptic curves with coefficients drawn from any number system made up of rational numbers plus simple irrational and complex numbers.

“The plan in advance [of the workshop] was just to see how close one could get to proving things,” Gee said. “I don’t think anyone really expected to prove the result.”

Extending the Bridge Meanwhile, a parallel story was unfolding for extending the bridge beyond elliptic curves. Calegari and Gee had been working with George Boxer (now at the École Normale Supérieure in Lyon, France) to tackle the case where the highest exponent in the Diophantine equation is 5 or 6 (instead of 3 or 4, the cases that were already known). But the three mathematicians were stuck on a key part of their argument.

Then, the very weekend after the “secret” workshop, Vincent Pilloni of the École Normale Supérieure put out a paper that showed how to circumvent that very obstacle. “We have to stop what we’re doing now and work with Pilloni!” the other three researchers immediately told each other, according to Calegari.

Within a few weeks, the four mathematicians had solved this problem too, though it took a couple of years and nearly 300 pages for them to fully flesh out their ideas. Their paper and the 10-author paper were both posted online in late December 2018, within four days of each other.

Soon after the secret workshop at the IAS, Frank Calegari (left), Toby Gee (center) and Vincent Pilloni, working with George Boxer (not pictured), found a way to extend the Langlands bridge beyond elliptic curves.

Frank Calegari, University of Chicago; Courtesy of Toby Gee; Arnold Nipoli

“I think they’re pretty huge,” Emerton said of the two papers. Those papers and the preceding building blocks are all “state of the art,” he said.

While these two papers essentially prove that the mysterious telepathy between Diophantine equations and automorphic forms carries over to these new settings, there’s one caveat: They don’t quite build a perfect bridge between the two sides. Instead, both papers establish “potential automorphy.” This means that each Diophantine equation has a matching automorphic form, but we don’t know for sure that the automorphic form lives in the patch of its continent that mathematicians would expect. But potential automorphy is enough for many applications — for instance, the Sato-Tate conjecture about the statistics of clock solutions to Diophantine equations, which the 10-author paper succeeded in proving in much broader contexts than before.

And mathematicians are already starting to figure out how to improve on these potential automorphy results. In October, for instance, three mathematicians — Patrick Allen of the University of Illinois, Urbana-Champaign, Chandrashekhar Khare of the University of California, Los Angeles and Jack Thorne of the University of Cambridge — proved that a substantial proportion of the elliptic curves studied in the 10-author paper do have bridges that land in exactly the right place.

Bridges with this higher level of precision may eventually allow mathematicians to prove a host of new theorems, including a century-old generalization of Fermat’s Last Theorem. This conjectures that the equation at the heart of the theorem continues to have no solutions even when x, y and z are drawn not just from whole numbers but from combinations of whole numbers and the imaginary number i.

The two papers carrying out the Calegari-Geraghty program form an important proof of principle, said Michael Harris of Columbia University. They’re “a demonstration that the method does have wide scope,” he said.

While the new papers connect much wider regions of the two Langlands continents than before, they still leave vast territories uncharted. On the Diophantine equations side, there are still all the equations with exponents higher than 6, as well as equations with more than two variables. On the other side are automorphic forms that live on more complicated symmetric spaces than the ones that have been studied so far.

“These papers, right now, are kind of the pinnacle of achievement,” Emerton said. But “at some point, they will just be looked back at as one more step on the way.”

Langlands himself never considered torsion when he thought about automorphic forms, so one challenge for mathematicians is to come up with a unifying vision of these different threads. “The envelope is being expanded,” Taylor said. “We’ve to some degree left the path laid out by Langlands, and we don’t quite know where we’re going.”

[trickydick] FUBHO: This is fascinating stuff, almost sounds like science fiction, only, as ...

trickydick — 11/1/2019 7:33:40 PM

FUBHO: This is fascinating stuff, almost sounds like science fiction, only, as you said, it's going to become commercialized soon. I'm new to some of these boards and I'm always looking for new opportunities for investments.

I may be stepping in here when huge volumes of information may have already been shared, over long periods, so my apologies if my inquiry is burdensome and amateurish.

.
So, my question is: Are you vested in this technology through the stock market? Do you see this specific type of computers to be a field to invest in? Is that best time already came and went? Is this technology so finite that investing in it wouldn't be worth the time to research it?

Just trying to expand my horizons.

I would appreciate any help and/ or direction you can give us. And, thank you.

[FJB] IBM DENIES GOOGLE QUANTUM SUPREMACY ibm.com On “Quantum Supremacy” | IB...

FJB — 10/23/2019 11:45:35 AM

IBM DENIES GOOGLE QUANTUM SUPREMACY

ibm.com

On “Quantum Supremacy” | IBM Research Blog
Edwin Pednault

October 21, 2019 | Written by: , John Gunnels, and Jay Gambetta

Categorized: Quantum Computing

Share this post:

Quantum computers are starting to approach the limit of classical simulation and it is important that we continue to benchmark progress and to ask how difficult they are to simulate. This is a fascinating scientific question.

Recent advances in quantum computing have resulted in two 53-qubit processors: one from our group in IBM and a device described by Google in a paper published in the journal Nature. In the paper, it is argued that their device reached “quantum supremacy” and that “a state-of-the-art supercomputer would require approximately 10,000 years to perform the equivalent task.” We argue that an ideal simulation of the same task can be performed on a classical system in 2.5 days and with far greater fidelity. This is in fact a conservative, worst-case estimate, and we expect that with additional refinements the classical cost of the simulation can be further reduced.

Because the original meaning of the term “quantum supremacy,” as proposed by John Preskill in 2012, was to describe the point where quantum computers can do things that classical computers can’t, this threshold has not been met.

This particular notion of “quantum supremacy” is based on executing a random quantum circuit of a size infeasible for simulation with any available classical computer. Specifically, the paper shows a computational experiment over a 53-qubit quantum processor that implements an impressively large two-qubit gate quantum circuit of depth 20, with 430 two-qubit and 1,113 single-qubit gates, and with predicted total fidelity of 0.2%. Their classical simulation estimate of 10,000 years is based on the observation that the RAM memory requirement to store the full state vector in a Schrödinger-type simulation would be prohibitive, and thus one needs to resort to a Schrödinger-Feynman simulation that trades off space for time.

The concept of “quantum supremacy” showcases the resources unique to quantum computers, such as direct access to entanglement and superposition. However, classical computers have resources of their own such as a hierarchy of memories and high-precision computations in hardware, various software assets, and a vast knowledge base of algorithms, and it is important to leverage all such capabilities when comparing quantum to classical.

When their comparison to classical was made, they relied on an advanced simulation that leverages parallelism, fast and error-free computation, and large aggregate RAM, but failed to fully account for plentiful disk storage. In contrast, our Schrödinger-style classical simulation approach uses both RAM and hard drive space to store and manipulate the state vector. Performance-enhancing techniques employed by our simulation methodology include circuit partitioning, tensor contraction deferral, gate aggregation and batching, careful orchestration of collective communication, and well-known optimization methods such as cache-blocking and double-buffering in order to overlap the communication transpiring between and computation taking place on the CPU and GPU components of the hybrid nodes. Further details may be found in Leveraging Secondary Storage to Simulate Deep 54-qubit Sycamore Circuits.

Figure 1. Analysis of expected classical computing runtime vs circuit depth of “Google Sycamore Circuits”. The bottom (blue) line estimates the classical runtime for a 53-qubit processor (2.5 days for a circuit depth 20), and the upper line (orange) does so for a 54-qubit processor.

Our simulation approach features a number of nice properties that do not directly transfer from the classical to quantum worlds. For instance, once computed classically, the full state vector can be accessed arbitrarily many times. The runtime of our simulation method scales approximately linearly with the circuit depth (see Figure 1 above), imposing no limits such as those owing to the limited coherence times. New and better classical hardware, code optimizations to more efficiently utilize the classical hardware, not to mention the potential of leveraging GPU-direct communications to run the kind of supremacy simulations of interest, could substantially accelerate our simulation.

Building quantum systems is a feat of science and engineering and benchmarking them is a formidable challenge. Google’s experiment is an excellent demonstration of the progress in superconducting-based quantum computing, showing state-of-the-art gate fidelities on a 53-qubit device, but it should not be viewed as proof that quantum computers are “supreme” over classical computers.

It is well known in the quantum community that we at IBM are concerned of where the term “quantum supremacy” has gone. The origins of the term, including both a reasoned defense and a candid reflection on some of its controversial dimensions, were recently discussed by John Preskill in a thoughtful article in Quanta Magazine. Professor Preskill summarized the two main objections to the term that have arisen from the community by explaining that the “word exacerbates the already overhyped reporting on the status of quantum technology” and that “through its association with white supremacy, evokes a repugnant political stance.”

Both are sensible objections. And we would further add that the “supremacy” term is being misunderstood by nearly all (outside of the rarified world of quantum computing experts that can put it in the appropriate context). A headline that includes some variation of “Quantum Supremacy Achieved” is almost irresistible to print, but it will inevitably mislead the general public. First because, as we argue above, by its strictest definition the goal has not been met. But more fundamentally, because quantum computers will never reign “supreme” over classical computers, but will rather work in concert with them, since each have their unique strengths.

For the reasons stated above, and since we already have ample evidence that the term “quantum supremacy” is being broadly misinterpreted and causing ever growing amounts of confusion, we urge the community to treat claims that, for the first time, a quantum computer did something that a classical computer cannot with a large dose of skepticism due to the complicated nature of benchmarking an appropriate metric.

For quantum to positively impact society, the task ahead is to continue to build and make widely accessible ever more powerful programmable quantum computing systems that can implement, reproducibly and reliably, a broad array of quantum demonstrations, algorithms and programs. This is the only path forward for practical solutions to be realized in quantum computers.

A final thought. The concept of quantum computing is inspiring a whole new generation of scientists, including physicists, engineers, and computer scientists, to fundamentally change the landscape of information technology. If you are already pushing the frontiers of quantum computing forward, let’s keep the momentum going. And if you are new to the field, come and join the community. Go ahead and run your first program on a real quantum computer today.

The best is yet to come.

Chief Architect for IBM Q Dmitri Maslov also contributed to this article.

[FJB] Math Breakthrough Speeds Supercomputer Simulations Andy Fell egghead.ucdavis.ed...

FJB — 10/20/2019 6:18:32 AM

Math Breakthrough Speeds Supercomputer Simulations
Andy Fell
egghead.ucdavis.edu /2019/10/18/math-breakthrough-speeds-supercomputer-simulations/

A breakthrough by UC Davis mathematicians could help scientists get three or four times the performance from supercomputers used to model protein folding, turbulence and other complex atomic scale problems.

“This is a big deal,” said Niels Gronbech-Jensen, professor of mathematics and of mechanical and aerospace engineering at UC Davis. “We are now able to do a broad class of simulations several times faster than what has been possible before.”

Simulation of a virus particle created with LAMMPS molecular dynamics software. New work from UC Davis will allow faster and more accurate simulations of atoms and molecules. (Image by Eindhoven University of Technology via Sandia National Lab.)

One of the new algorithms has been incorporated into the Sandia National Laboratory molecular dynamics suite, LAMMPS, which is used worldwide for studies in biochemistry, materials science and other fields.

Newton’s equations describe how systems change over time. In the early twentieth century, physicist Paul Langevin developed equations that add friction and noise to Newton’s equations in order to describe a system in thermal balance. But it was only with the development of computers that it became practical to use these equations to study how large ensembles of atoms and molecules behave. That methodology, called molecular dynamics, was pioneered by, among others, Edward Teller and Bernie Alder of the Lawrence Livermore National Laboratory and the UC Davis Department of Applied Science.

Molecular dynamics simulations are now widely used in applications such as materials science and pharmaceutical research.

The timestep problemIn adapting Newton’s and Langevin’s equations to run on digital computers, scientists had to make an important change. They had to break the equations into discrete timesteps.

“The time step makes the system behave differently,” Gronbech-Jensen said.

The shorter the timesteps, the closer the simulation will be to reality, where systems change continuously. But with short timesteps it takes longer to complete a simulation. With larger timesteps, however, results can start to deviate from reality.

“We are in a squeeze between getting somewhere and being accurate,” Gronbech-Jensen said.

Molecular dynamics simulations essentially describe the movements and interactions of a lot of particles. A few years ago, Gronbech-Jensen’s research group found a way to accurately calculate the thermal distributions of positions of particles in a simulation regardless of the timestep. Over the past year, they have figured out that they can obtain accurate thermal distributions for the particle velocities as well, thereby getting a complete and accurate statistical description of a molecular ensemble simulated at large time steps.

The new algorithm allows scientists to run simulations with bigger timesteps without losing statistical accuracy. This could effectively increase computing power three- to four-fold or more, Gronbech-Jensen said – a feature that is particularly impactful for simulations that are currently challenging the most powerful supercomputers in the world.

The new capability is now freely available to use through the LAMMPS molecular dynamics suite.

Gronbech-Jensen said it’s gratifying to see his team’s work go into wide use.

“It’s great to see our work getting to the point of having tangible impact,” he said.

More information Accurate configurational and kinetic statistics in discrete-time Langevin systems (Molecular Physics)

Complete set of stochastic Verlet-type thermostats for correct Langevin simulations (Molecular Physics)

[DinoNavarre] Will do.....Thanks.

DinoNavarre — 9/19/2019 6:54:07 PM

[FJB] There many, many companies like that in China. You should ask about miners here...

FJB — 9/19/2019 5:39:11 PM

There many, many companies like that in China. You should ask about miners here ...
Subject 59919