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[BeenRetired] Amazon's data center breakthrough might change the future of cloud storage [gra...

BeenRetired — 6/16/2026 10:38:34 AM

Amazon's data center breakthrough might change the future of cloud storage

BGR

Amazon's data center breakthrough might change the future of cloud storage
Story by Alan Bradley
Jun 14 • 4 min read • Updated 1d ago

Key takeaways

RNG Technology: Amazon's Resilient Network Graphs (RNG) use randomized cable connections via ShuffleBox and the Spraypoint algorithm to improve network efficiency, reduce hardware needs, and boost throughput by 33%.
Energy Efficiency: The new system cuts power usage by 40% and requires 69% fewer routers and switches, helping data centers lower environmental impact and reduce strain on power grids.
Network Innovation: Replacing traditional fat-tree networks, RNG allows data to flow across multiple random paths, minimizing congestion and improving reliability with optical circuit switching (OCS).

Amazon, a heavy investor in AI, has pioneered a technology it says will make its data centers both more resilient and more power efficient. A 2026 report by Wired shared that Amazon claims the new architecture will allow the company to use 69% fewer routers and switches and 40% less power at its massive Amazon Web Services (AWS) data centers, yet provide 33% better throughput.
The core of the breakthrough is called resilient network graphs, or RNG. It's a way to use random cable connections to make a network work more efficiently. In it are two key innovations: On the hardware side is a device called a ShuffleBox, which randomizes physical cable connections between network components to make the network structure more efficient. It pairs with software called Spraypoint, a custom traffic-routing algorithm specifically designed to work within the RNG design.

RNG relies on a theory pioneered by Hungarian mathematicians back in 1959, called random network graphs, specifically the Erdos–Rényi model. To understand it, it helps to picture a graph with several dots on it. The dots are connected randomly but, importantly, according to fixed probability rules. This means you get different final graphs every time, but also ones whose statistical properties can be predicted. While RNG is quasi-random rather than truly random, the random elements are governed by strict precepts. The resulting improvement in efficiency means less power-hungry hardware, which in turn means less power consumption across the network, a vital consideration as data centers struggle to find sources to meet their voracious appetite for power without overwhelming electric grids and infrastructure.

Read more: Amazon Unclaimed Packages Can Be Bought By Anyone — Here's How

How the RNG system compares
A typical data center uses a "fat tree" network structure. Data flows up and down a stack, with fat nodes at the top. Those fat nodes are powerful server clusters capable of breaking up bottlenecks created by the linear nature of the "tree," which is a stack mostly made up of switches (which move data within a network) and routers (which move data between networks). Down near the "roots," the pathways get thinner. Fat-tree structures require masses of cabling and tons of hardware, and while they're generally reliable, they're not particularly efficient.

Instead of the fat tree model, where traffic has to flow down a small number of fixed paths and can get jammed up, a random network graph could allow them to move across a larger number of random routes, creating many alternative paths between any two points. The challenge is implementing that idea with physical cabling. Enter the ShuffleBox, which can shuffle physical cables randomly, according to the random network graph concept. An important part of the design is optical circuit switching (OCS). This method transmits data from a start point to an end point purely as light inside fiber optic cables. It's more efficient than traditional data transmission because, unlike the conventional method, it doesn't require the data to stop at various points, get translated into electrical energy, then translated back into light at the next node or destination.

Spraypoint helps by doing what it says on the tin: rather than sending data packets along one best path, it "sprays" them randomly across multiple neighboring routers. The packets are then picked up by a number of intermediate routers standing by to send them on to the proper destination. It spreads traffic out to avoid congestion and reduces crowded hotspots.

Why the breakthrough is so important
Reducing the power draw of data centers is vital to ensuring their construction doesn't decimate the environment and power grid. For example, Syracuse stated that there are currently 30 data centers seeking construction permits in New York State. If all of them are built, they'll use more power than the nation of Ireland, putting additional stress on an aging grid already badly deteriorating after years of deferred maintenance and underinvestment.

It's a common issue nationwide. Analysis by Bloomberg showed that customers as distant as an hour's drive from new data centers could expect to pay up to 267% percent more for utility bills than five years prior. That means nearly tripling utility costs that are already skyrocketing to record highs. While hardly a panacea, Amazon's RNG technology could make a significant impact, given that the company uses a staggering amount of energy and was revealed in 2025 to have twice the number of active data centers than previously estimated (per SourceMaterial with Bloomberg).

The same report points out that Amazon's data centers are driving the construction of new gas plants and extending the life of existing coal plants that may otherwise have been retired. The size of data centers is also concerning for nearby residents, with Meta's Louisiana data center measuring nearly 70 football fields in length. The environmental impact is also significant. A separate 2025 SourceMaterial report illustrated how Amazon, alongside Google and Microsoft, is operating (and continuing to construct) data centers, which rely on huge amounts of water for cooling, in some of the driest areas of the world.

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[BeenRetired] Qualcomm stock rises on AI chip push, Tenstorrent deal speculation Qualcomm ...

BeenRetired — 6/16/2026 10:14:52 AM

Qualcomm stock rises on AI chip push, Tenstorrent deal speculation
Qualcomm stock rises on AI chip push, Tenstorrent deal speculation

Qualcomm gains as AI ambitions and Tenstorrent deal talks boost stock.
J.P. Morgan sees Qualcomm data-center revenue topping $3 billion by 2027.
CEO says AI agents and smart glasses could drive future growth.

Qualcomm QCOM shares moved higher on Tuesday as investors focused on the chipmaker's expanding artificial intelligence ambitions.

Investors also reacted to reports of a potential acquisition and expectations for new details on the company's data-center strategy at an upcoming investor event.

The stock gained about 3% in premarket trading to $228.09, extending a strong rally that has seen shares rise roughly 68% over the past three months.

Investors appear increasingly focused on Qualcomm's efforts to diversify beyond its traditional smartphone business and establish a larger presence in the rapidly growing market for AI infrastructure and data-center chips.

Qualcomm reportedly explores Tenstorrent acquisition
A major source of investor interest emerged after a report from The Information indicated that Qualcomm is in discussions to acquire privately held AI chip startup Tenstorrent for between $8 billion and $10 billion.

Tenstorrent develops AI accelerators designed for model training and inference workloads and has positioned its technology as an alternative to traditional graphics processing units used in AI computing.

The potential acquisition could also provide Qualcomm with access to Tenstorrent Chief Executive Officer Jim Keller, one of the semiconductor industry's most prominent chip architects.

Keller previously held engineering roles at AMD, Apple, and Tesla.

The reported talks come as Qualcomm continues to expand its AI-related capabilities.

Last year, the company completed its acquisition of UK-based Alphawave Semi for $2.4 billion, adding technology designed to improve inter-chip data-transfer speeds.

While no transaction has been announced, investors view the potential deal as another sign of Qualcomm's commitment to strengthening its position in the AI hardware market.

Investor day expected to highlight data-center ambitions
Attention is also turning toward Qualcomm's investor day scheduled for June 24.

J.P. Morgan analyst Samik Chatterjee said investors are expecting additional details regarding Qualcomm's custom AI processors and data-center strategy.

The analyst believes the company could outline a path to more than $3 billion in data-center revenue by fiscal 2027, with that figure potentially expanding to $35 billion by fiscal 2031.

“We are placing Qualcomm shares on Positive Catalyst Watch driven by expectations for targets outlined at the investor day to exceed investor expectations, even though we remain Neutral-rated awaiting evidence of execution to the outlined opportunities in an increasingly competitive market,” Chatterjee wrote in a recent research note.

Investors are also anticipating the announcement of a major customer for Qualcomm's custom data-center chips.

The company's growing focus on AI infrastructure has helped offset concerns surrounding its smartphone business and increasing competition in the PC chip market from rivals, including Nvidia.

Qualcomm is trading above 20 times its projected earnings in the next year, making it a cheaper option among chip stocks.

For comparison, Arm Holdings trades around 175 times its projected earnings.

CEO outlines broader AI ecosystem vision
Qualcomm Chief Executive Officer Cristiano Amon recently discussed the company's broader AI strategy during an appearance on CNBC's The Tech Download podcast.

According to Amon, Qualcomm currently has more than 40 AI-enabled device designs in development, including smart jewelry, camera-equipped audio wearables, pins, and watches.

He described smart glasses as a category that could eventually reach smartphone-like scale.

Amon noted that annual shipments are already measured in the "tens of millions" and could eventually grow into the "hundreds of millions."

Amon also highlighted the growing importance of agentic AI, which can perform tasks across multiple applications and platforms.

“Those agents are going to be the new app,” he said.

PS

Amon has grand ambitions...just like all Leading-Edge guys...including Su.

[BeenRetired] EUV enables 2D transistor. ASML, TSMC, and imec Achieve 300 mm Integration of 2...

BeenRetired — 6/16/2026 9:57:57 AM

EUV enables 2D transistor.

ASML, TSMC, and imec Achieve 300 mm Integration of 2D-Material Transistors with 50 nm Pitch | TechPowerUp
Monday, June 15th 2026
ASML, TSMC, and imec Achieve 300 mm Integration of 2D-Material Transistors with 50 nm Pitch
Press Release by Nomad76 Yesterday, 09:20 Discuss (2 Comments)
This week, at the 2026 IEEE/JSAP Symposium on VLSI Technology and Circuits, imec, a world-leading research and innovation hub in advanced semiconductor technologies, in partnership with the lithography solution provider ASML, and semiconductor foundry TSMC, presents a novel, robust and scalable 300 mm integration route for 2D-material based n and pFETs. For the first time, scaled nFETs (implementing MoS2 as the channel material) and pFETs (either WS2 or WSe2-based) with 50 nm contacted poly pitch (CPP) could be demonstrated, with good current-voltage characteristics. These results represent a crucial step in the lab-to-fab transition of 2D-material based transistors, envisioned for ultra-scaled logic as well as for back-end and wafer backside applications.

2D transition metal dichalcogenides (TMDs, such as MoS2, WS2, and WSe2) have the potential to extend and augment the logic scaling technology roadmap. When integrated as atomically thin conduction channels replacing Si, these materials enable high-performance scaled transistors - attractive for ultra-scaled logic as well as for back-end-of-line and wafer backside applications. They owe this promise to their good electrostatic channel control while maintaining acceptable carrier mobilities, even at ultra-scaled gate and channel lengths. But the path to industrial adoption has so far been hampered by the lack of a 300 mm integration route that can offer TMD-based n and pFETs at industry-relevant dimensions, while preserving the performance that has extensively been demonstrated on a lab scale.

ASML, TSMC and imec and now present a scalable, back-end-compatible 300 mm integration approach for TMD-based n and pFETs, which has led to three key outcomes: (1) scaled n and pFETs with 50 nm contacted poly pitch (CPP) - a world first; (2) very low off current (Ioff) at zero gate voltage (Vg=0 V) for both transistor polarities; and (3) pFETs with WSe2 channel performing close to record lab-based devices. With 94% operational transistors (i.e., with Imax/Imin >105), the CMOS-like integration approach - with n and pFETs integrated on the same 300 mm wafer - is proven to be robust and stable. The proposed process flow is applicable to 2D channel materials other than MoS2, WS2, and WSe2.Gouri Sankar Kar, VP R&D compute and memory device technologies at imec: "Transistors based on 2D TMD materials are typically optimized for small channel lengths. However, they usually have a large contact area to keep the contact resistance as low as possible, hindering further scaling. For the first time, we achieved 50 nm CPP - a metric determined by both the gate length and source/drain contact length - without affecting the performance of the 2D n and pFETs. The use of single-patterning EUV lithography, optimized in close collaboration with ASML, was key in enabling the scaled CPP."The scaled transistors show good current-voltage characteristics, with pFETs performing nearly as well as the best performing lab-based devices - addressing a long-standing challenge for TMD transistors. In addition, electrical results show that both transistor polarities turn off when the gate voltage (Vg) is set to 0 V. "This ideal behavior can be ascribed to the use of an innovative 'reverse' thin-film transistor (TFT) fabrication flow," explains Gouri Sankar Kar. "Unlike conventional 2D-material based transistors, our n and pFETs have bottom contacts and an overlapping deposited gate. This is realized by transferring the TMD channel material onto already pre-patterned tungsten (W)-filled trenches working as the contacts. "

Highlighting the strategic importance of the research work, Dr. Min Cao, TSMC's Vice President and CTO remarked, "Our research collaboration is instrumental in pushing the boundaries of semiconductor innovation. The focus is on de-risking and accelerating the 'lab to fab' transition, ensuring that groundbreaking discoveries - especially in these novel channel materials - could be rapidly and efficiently integrated into advanced manufacturing, and ultimately deliver cutting-edge solutions."

[qoute]"2D TMD materials could potentially enable much smaller and higher-performance transistors than those based on silicon, but 2D-channel devices that have been demonstrated so far using 300 mm processes are actually fairly large, and patterned using older lithographic technologies. Thanks to the much sharper resolution of EUV lithography, we were able to create TMD transistors with channel lengths as small as 28 nm, and at a pitch compatible with the most advanced transistor nodes." added Etienne De Poortere, Director Technology Development Center Europe of ASML.[/quote]

ASML, TSMC, and imec Breakthrough in 2D-Material Transistor IntegrationASML, TSMC, and imec have jointly demonstrated a major step toward manufacturing 2D-material-based transistors by showing a scalable, 300?mm integration route for both n-type and p-type field-effect transistors (FETs) www.newswiretoday.com.

Key Achievements

Scaled nFETs and pFETs: For the first time, devices with 50?nm contacted poly pitch (CPP) were fabricated, a world first for 2D-material transistors www.newswiretoday.com.
Channel materials:
- nFETs used MoS2 as the channel material.
- pFETs used WS2 or WSe2, with WSe2 achieving performance close to record lab results www.newswiretoday.com.
Performance:
- Very low off-current (Ioff) at zero gate voltage for both polarities.
- pFETs with WSe2 channels matched or exceeded earlier record lab performance www.newswiretoday.com.
Back compatibility: The process is designed to integrate with existing 300?mm CMOS fabs, enabling a smoother transition from lab-scale research to high-volume manufacturing www.newswiretoday.com.

Why This Matters2D transition metal dichalcogenides (TMDs) like MoS2, WS2, and WSe2 can replace silicon in transistors, enabling ultra-scaled logic and new applications such as back-end-of-line (BEOL) and wafer backside integration. They offer:

High electrostatic channel control even at extreme gate/channel lengths.
High carrier mobility for performance.
Potential to extend the CMOS scaling roadmap beyond silicon limits www.newswiretoday.com.

Path ForwardThis collaboration addresses long-standing challenges in 2D-FET manufacturing, including:

High-quality 2D-material deposition.
Low-resistance source/drain contacts.
Robust gate stack integration (e.g., HfO2 dielectric for WSe2 channels, solved via synthetic bilayer and interfacial oxide formation in earlier imec–TSMC work www.imec-int.com+1).
300?mm fab compatibility for industrial adoption www.newswiretoday.com.

In summary: ASML, TSMC, and imec’s breakthrough demonstrates that 2D-material transistors are moving from the lab toward manufacturable, high-performance devices, with potential to power next-generation logic and novel chip architectures.

[BeenRetired] "memory chip shortages will last throughout 2027 and beyond" Some of Sandis...

BeenRetired — 6/16/2026 9:48:27 AM

"memory chip shortages will last throughout 2027 and beyond"

Some of Sandisk's competitors have warned that ongoing memory chip shortages will last throughout 2027 and beyond. Sandisk is already sold out of memory products through 2026 and is seeing heightened demand for 2027.

The SanDisk rally isn't over yet

[BeenRetired] Applied Materials unveils deposition, selective etch systems to advance 3D chip ...

BeenRetired — 6/16/2026 9:46:41 AM

Applied Materials unveils deposition, selective etch systems to advance 3D chip scaling
Applied Materials unveils deposition, selective etch systems to advance 3D chip scaling

16h

Applied Materials ( AMAT) on Monday said it has introduced two new chipmaking systems to advance 3D chip scaling.
The new deposition and etch systems will help chipmakers extend scaling in logic and memory to deliver higher performance, improved energy efficiency, and better manufacturing yield for next-generation AI chips, the company said.
Applied said that the surge in AI compute is accelerating the industry’s transition to advanced 3D device architectures, including gate-all-around transistors and high-layer-count 3D NAND, and to help address this challenge, it has introduced Centris Spectral SiN ALD and Producer Selectra Mo Etch.
Centris Spectral SiN ALD leverages microwave plasma technology to deliver uniform silicon nitride deposition in challenging 3D structures, while Producer Selectra Mo Etch selectively removes molybdenum for wordline separation to enable 3D NAND scaling.
The company said the new systems are being used by leading logic and memory chipmakers for advanced node manufacturing.
California-based Applied Materials closed over 3% higher on Monday.
Press release

[BeenRetired] TSMC reportedly goes after Samsung's one remaining chip advantage TSMC reportedl...

BeenRetired — 6/16/2026 9:10:53 AM

TSMC reportedly goes after Samsung's one remaining chip advantage
TSMC reportedly goes after Samsung's one remaining chip advantage

Story by Justin Diaz • 18h

When it comes to chip production, TSMC has the advantage over Samsung overall, but there is one area where Samsung reportedly reigns supreme, and that’s with the panel-level-packaging technique that it created to help with its chips production processes. TSMC now reportedly wants to take this advantage away from Samsung, and is said to be making that attempts by starting its own panel-level-packaging processes.

Panel-level packaging, or PLP, is how Samsung is currently producing its semiconductor chips. This packaging process sets up chips on a rectangular as opposed to the circular wafers that most companies use. The rectangular shape allows for more space to actually use for chip production. Whereas the circular wafer shape ends up with a little wasted space around the edges that can’t be used. In other words, PLP can allow for a better yield, and thus more chips.

TSMC to remove the Samsung chip advantage with its own PLP process
According to reports from etnews (via SamMobile), TSMC is looking to start mass production of chips via the panel-level-packaging manufacturing technique soon. This change to PLP over the more common wafer process could give TSMC yet another big step up over its competitors. TSMC has used this technology before, and started development with it back in 2024. Though this is later than when Samsung started, which is how Samsung has been able to really pull ahead in this particular area.

Thew report doesn’t specific dates for the mass production but it does give a general time frame. Sometime in 2027 is when TSMC is expected to begin its mass production with the PLP method. That gives Samsung plenty of time to continue producing chips this way without competition from TSMC. Whether or not that helps Samsung in the long run is still unclear. With this being its one major advantage though, Samsung will need to come up with other ways to maintain some form of a lead in this business against TSMC.

The post TSMC reportedly goes after Samsung's one remaining chip advantage appeared first on Android Headlines.

[BeenRetired] Why IMEC’s new 6G chip breakthrough is exactly what Nvidia’s Jensen Huang is loo...

BeenRetired — 6/16/2026 9:04:57 AM

Why IMEC’s new 6G chip breakthrough is exactly what Nvidia’s Jensen Huang is looking for right now
Why IMEC’s new 6G chip breakthrough is exactly what Nvidia’s Jensen Huang is looking for right now

Story by Rahim Amir • 14h

Belgium-based IMEC is the world's largest independent research lab for chip-centric technologies
It recently unveiled a breakthrough in its III-V chiplet integration on 300mm silicon, enabling it to pack high-performance chips into a denser configuration while offloading passive components onto a silicon interposer
The breakthrough allows for AI to exist at scale by scaling up efficiency and bringing down costs

NVIDIA CEO Jensen Huang has been very vocal about where the next frontier for AI lies: telecom.

The contention is that as the next generation of wireless communication is ushered in, the lines between software and hardware will be further blurred, with every radio access network essentially behaving as an AI computer.

The issue, however, centers around adoption: How cheap, accessible, and scalable the underlying technology will be is key, and it is one that IMEC might have at least partially solved.

An efficiency and adoption problem to solve
NVIDIA is not exactly a passive observer in telecom, however. It has pumped $1 billion into the Finnish telecom giant, Nokia, for a 2.9% stake. It has also cobbled together a coalition of global telecom leaders committed to building on AI-Native platforms to power 6G.

It sees telecom as the next large growth sector in terms of both revenue and scale for its own AI ambitions and also identifies it as a crucial driver for both the software layer and the hardware stack it currently sells.

Unlike Nvidia, IMEC is a non-profit that focuses on research and development and emphasizes commercializing its research, which has led it to partner with over 600 global industry players.

Désiré Athow, managing editor of TechRadar Pro, described IMEC as the United Nations of the silicon world, a place where the world's most valuable tech companies can meet, discuss, and shape the technology pipeline for the next decade.

Xiao Sun, principal member of technical staff at IMEC, indicated that there is much more that needs to be done: “With this work, we demonstrate a uniquely integrated platform that brings together performance, scalability, and manufacturability. Our next priority is to further advance the platform’s technology readiness, and to enable support for low-volume manufacturing – helping our partners more easily develop and scale next-generation RF systems.”

The crux is that out of any breakthrough from what many consider the chip lab of the world, one that enables cheaper, more scalable 6G adoption, has widespread ramifications across the AI industry and addresses the need of the hour, and Nvidia and industry rivals alike will be keeping an eye on matters as everyone searches for the next accelerator for AI.

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PS
Rolling MoAPS ONLY picks up steam...driven by Leading-Edge guys.

[BeenRetired] Amazon signs multibillion-dollar Corning deal to build the next generation of ca...

BeenRetired — 6/15/2026 11:27:26 AM

Amazon signs multibillion-dollar Corning deal to build the next generation of cables
Amazon signs multibillion-dollar Corning deal to build the next generation of cables

Story by Rahim Amir • 1d

Amazon signs agreement with Corning to procure fiber optic cables and networking components
The move is expected to create hundreds of construction jobs in addition to the 1000 it creates at Corning's facilities in North Carolina
Move comes as Amazon announces more than $20 billion investment into the state to create 26,000 jobs

Amazon has announced a multi-year, multi-billion-dollar agreement with Corning to supply its data center needs as it capitalizes on an AI-driven boom in demand.

The move, which creates manufacturing and construction jobs, also expands Corning's Fiber Optic Technician Training Program at Catawba Valley Community College, signaling an increased demand for technical workers in the fiber-optic industry.

Amazon has already committed to $10 billion in cloud infrastructure investments in North Carolina, investing over $20 billion in the state in projects it says have directly contributed to the creation of 26,000 jobs.

Amazon's glass obsession: bandwidth is key
The agreement comes weeks after AWS (Amazon Web Services) showcased Random Network Graph architecture, a fiber-optic network design that arranges cables in a semi-random configuration to boost bandwidth and reliability between servers.

The design considerably increases demand for fiber-optic cable and connectivity while solving one of AI's biggest challenges as models and data centers grow larger: reliable bandwidth.

Corning makes for an ideal partner for most AI data center companies looking to build out infrastructure: it is one of the world's largest fiber-optic manufacturers, is a US-based company, and offers cutting-edge fiber-optic technology all in one package. The 175-year-old glass company is up 94.72% Year-to-date (YTD) as investors continue to look for indirect beneficiaries of the AI trade amid unabated spending.

Amazon's move is not an isolated one, even as it marks a multi-billion-dollar investment in fiber optics for Corning. Nvidia has already been here first, backing the construction of 3 new optical equipment facilities and investing as much as $3.2 billion in the company's shares to finance what it says is a "10x increase" in its US-based optical connectivity manufacturing capacity.

"Amazon's investments in North Carolina have created more than 26,000 jobs across the state. This multibillion-dollar agreement with Corning continues that commitment, channeling investment into American manufacturing and creating 1,000 new jobs at their facilities near our data centers," said Matt Garman, CEO of AWS.

"We're also partnering to train North Carolinians for highly skilled roles in fiber optics and fusion splicing. These long-term investments create long-term careers and real opportunity in the communities where we operate."

Like this article? For more stories like this, follow us on MSN by clicking the +Follow button at the top of this page.

[BeenRetired] "50-fold reduction in contact resistance" with 17X on-state current

BeenRetired — 6/15/2026 9:44:33 AM

[BeenRetired] Ultra-thin semiconductors overcome performance limits with localized thick-conta...

BeenRetired — 6/15/2026 9:42:47 AM

Ultra-thin semiconductors overcome performance limits with localized thick-contact design
Ultra-thin semiconductors overcome performance limits with localized thick-contact design

Story by Science X staff
• 1w •
3 min read

Schematic of the tellurium transistor employing a raised source/drain structure, and the improved transfer characteristics resulting from reduced contact resistance (demonstrating an over 17-fold increase in on-state current). Credit: POSTECH

As semiconductor chips become increasingly thinner, the components inside chips are locked in a fierce race to achieve the ultimate ultra-thin state. However, this has presented a structural limitation: the thinner the device, the harder it is for electricity to flow.

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Recently, a research team at POSTECH (Pohang University of Science and Technology) successfully resolved this issue through a simple yet innovative approach: "thickening only the necessary parts."

The research team, led by Professor Byoung Hun Lee from POSTECH's Department of Electrical Engineering and the Department of Semiconductor Engineering, has developed a technology that dramatically lowers contact resistance by redesigning the metal-semiconductor contact structure in ultra-thin tellurium (Te) transistors.

The work is published in ACS Nano.

Why ultra-thin chips face limits
With the rapid advancement of artificial intelligence (AI) and high-performance computing, the volume of data that semiconductors must process is surging. Consequently, the time and energy loss occurring between the "logic" (which handles computations) and "memory" (which stores data) have been identified as a major bottleneck.

To address this, 3D integrated structures that stack logic and memory vertically are gaining significant traction as a next-generation technology. Fabricating these structures requires devices that can operate stably even at temperatures below 400°C.

Tellurium (Te) is highly regarded as a strong candidate for semiconductor channel material due to its high charge mobility, room-temperature stability, and low-temperature processability. However, its narrow band gap makes it prone to "leakage current," where current leaks even when the transistor is turned off. To minimize this, the channel must be fabricated to an ultra-thin thickness of under 5 nanometers (nm) to precisely control electron transport.

The thin-channel performance dilemma
The dilemma arises because when the channel becomes too thin, electron transport across the interface between the metal electrode and the semiconductor becomes severely restricted. A Schottky barrier—an energy barrier that electrons must cross between the metal and semiconductor—grows larger as the channel gets thinner.

Ultimately, while researchers could reduce leakage current, doing so simultaneously increased contact resistance, significantly degrading device performance.

Thickening only where it matters
To overcome this, the POSTECH team applied the "Raised Source and Drain (RSD)" structure, a technique conventionally used in silicon processes. The core idea is to deposit additional tellurium to thicken only the areas directly in contact with the electrodes where the current enters and exits (the source and drain).

By keeping the current-flowing channel at a thin 4 nm to suppress leakage current while adding extra tellurium to the sections in contact with the metal electrodes, the team allowed the current to flow with significantly improved efficiency.

Results, scalability, and future impact
Experimental results demonstrated that devices utilizing this structure experienced a dramatic 50-fold reduction in contact resistance, dropping from 97.5 kO·µm to 1.7 kO·µm. Furthermore, in an extreme environment of -196°C, the on-state current when the device was fully turned on increased by more than 17 times.

The team effectively succeeded in simultaneously achieving both low resistance and high performance within an ultra-thin structure. Notably, this technology can be implemented through a large-area, low-temperature deposition process known as sputtering, ensuring the high scalability required for actual semiconductor mass production.

"We have broken through the chronic dilemma of ultra-thin semiconductors—where thinner channels traditionally resulted in higher resistance—with a novel band engineering approach called 'localized thickness control,'" said Professor Byoung Hun Lee of POSTECH.

"We expect this to become a core platform technology that can be widely applied not only to tellurium but also to enhancing the performance of various 2D and ultra-thin semiconductor devices, ultimately accelerating the realization of next-generation 3D integrated circuits."

More information: Minjae Kim et al, Thickness-Modulated Band Engineering for Low-Resistance Contacts in Ultrathin Tellurium Transistors, ACS Nano (2026). DOI: 10.1021/acsnano.5c18395

[BeenRetired] Nvidia 'reinvents PC' with AI chip that replaces mouse and keyboard [graphic] T...

BeenRetired — 6/14/2026 5:17:38 PM

Nvidia 'reinvents PC' with AI chip that replaces mouse and keyboard

The Independent

Nvidia 'reinvents PC' with AI chip that replaces mouse and keyboard
Story by Anthony Cuthbertson
Jun 02 • 2 min read • Updated 1w ago

Key takeaways

AI Superchip: The RTX Spark embeds personal AI agents directly on laptops, enabling tasks to be performed autonomously without cloud computing.
Performance Specs: Offers up to 1 petaflop of compute and 128GB memory, designed exclusively for Windows devices.
Industry Impact: Available on laptops from Asus, Dell, HP, Lenovo, MSI, Microsoft, with Acer and Gigabyte coming soon; Nvidia positions this as a PC reinvention, akin to the smartphone revolution.

Nvidia has unveiled a new AI chip for laptops that the company claims will completely change how people use computers.

The RTX Spark ‘superchip’ is designed to embed personal artificial intelligence agents directly onto the device, without relying on cloud computing.

The $5 trillion US chip firm claims the RTX Spark is powerful enough to support on-device AI agents that can autonomously carry out tasks across applications – without the user needing to touch the mouse or keyboard.

“You set the objective. The machine handles the rest,” the firm’s marketing materials state. “There’s intelligence on both sides of the keyboard now.”

The new chip comes with up to 1 petaflop of compute and 128GB of memory and will only work with devices running Microsoft’s Windows operating system.

Nvidia founder and CEO Jensen Huang compared the arrival of RTX Spark to the advent of the smartphone, turning a computer from a tool to a teammate.

“The PC is being reinvented,” Mr Huang said at the Computex conference in Taiwan on Monday.

“For forty years, you launched apps. Click. Type. With RTX Spark and Microsoft Windows, you ask – and the PC does the work... This is the new PC. The personal AI computer.”

The RTX Spark chip will be available on Windows laptops built by Asus, Dell, HP, Lenovo, MSI and Microsoft – with models from Acer and Gigabyte expected to follow.

“Our goal is to deliver unmetered intelligence to every home and every desk with Windows,” said Microsoft CEO Satya Nadella.

“RTX Spark marks a real breakthrough towards that vision.”

The AI boom in recent years has seen Nvidia rise to become the world’s most valuable company, with the company’s market cap rising more than 10-fold since the launch of ChatGPT in 2022.

Nvidia’s share price rose a further six per cent following the unveiling of its latest RTX Spark chip.

The Independent is the world’s most free-thinking news brand, providing global news, commentary and analysis for the independently-minded. We have grown a huge, global readership of independently minded individuals, who value our trusted voice and commitment to positive change. Our mission, making change happen, has never been as important as it is today.

PS
Client Compute highly competitive.
Great for ASML.

[BeenRetired] Samsung Electronics Begins Shipment of Industry-First HBM4E Samples Shannon Davi...

BeenRetired — 6/14/2026 12:10:17 PM

Samsung Electronics Begins Shipment of Industry-First HBM4E Samples
Shannon Davis
2 weeks ago

Samsung Electronics, a global leader in advanced memory technology, has begun shipping the industry’s first 12-layer HBM4E samples to major global customers, further strengthening its leadership in the next-generation HBM market.

Following the industry’s first mass production and commercial shipment of its industry-leading HBM4 earlier this year, Samsung now extends its HBM roadmap with the introduction of HBM4E samples, addressing the rapidly evolving demands of AI computing and hyperscale infrastructure.

“Following the successful mass production of HBM4, Samsung has once again demonstrated its distinct technological edge with HBM4E,” said Sang Joon Hwang, Executive Vice President and Head of Memory Development at Samsung Electronics. “Through our advanced manufacturing capabilities and preemptive infrastructure investments, we will continue to drive the growth of the global AI memory market.”

Samsung’s HBM4E delivers a stable pin speed of 14 gigabits-per-second (Gbps), with performance scalable up to 16Gbps to support increasingly intensive data processing requirements. This represents more than a 20% increase over its HBM4, while delivering memory bandwidth of up to 3.6 terabytes-per-second (TB/s) per stack, helping maximize computing performance for large language models (LLMs) and next-generation AI systems.

Samsung’s 12-layer HBM4E is offered in a 48-gigabyte (GB) capacity, representing more than a 30% increase over the previous generation, with plans to expand the lineup to include 32GB (8-layer) and 64GB (16-layer) configurations in accordance with customer requirements.

The HBM4E sets itself apart by taking full advantage of Samsung’s comprehensive semiconductor capabilities and leveraging the same leading-edge technologies refined through the company’s HBM4 production experience. This includes the industry’s most advanced 6th-generation 10-nanometer (nm)-class DRAM process---EUV---(1c) and Samsung Foundry’s 4nm logic base die, allowing the HBM4E to secure enhanced process stability and manufacturability.

Design and process optimization across both memory and logic architectures of Samsung’s HBM4E also improves performance, power efficiency and yield.

In particular, advanced low-power design technologies and optimized packaging structures improved energy efficiency by 16% and thermal resistance characteristics by more than 14% compared to the previous generation. These enhancements also enable more effective heat dissipation, allowing prolonged reliability and lower energy consumption in next-generation data centers with intensive workloads.

Samsung plans to begin mass production for HBM4E aligned with customer schedules, following initial sample shipments and optimization.

Feedback from global customers on Samsung’s HBM4, introduced in February, have been highly positive, especially for its performance and energy efficiency. The HBM4 was the first in the industry to enter mass production and has successfully set the bar for the industry with speeds of 11.7Gbps in its system in package (SiP) tests.

As stable supply of Samsung’s HBM4 continues to grow, the company’s latest HBM4E using the same combination of core and base die is anticipated to enter mass production to further accelerate innovation in next-generation AI systems. With its comprehensive portfolio spanning memory, foundry, logic design and advanced packaging, Samsung will continue to ensure a stable semiconductor supply for the booming AI market.

PS
Memory and Storage bonanza JUST started.

[BeenRetired] Global Semiconductor Market Surges Beyond $1.5T 2026 Shannon Davis 2 weeks ago [...

BeenRetired — 6/14/2026 11:46:34 AM

Global Semiconductor Market Surges Beyond $1.5T 2026
Shannon Davis
2 weeks ago

Following exceptionally strong results in late 2025 and early 2026, the global semiconductor market is now projected to grow 90 percent in 2026, reaching USD 1.51 trillion.

The sharp upward acceleration is overwhelmingly driven by the Memory segment, which is forecast to surge by around 250 percent year over year, reaching more than USD 800 billion in 2026. Continued strong demand for AI infrastructure, high-bandwidth memory (HBM)---All 3 RAM oligarchs are EUV---, and accelerated computing platforms remains the primary growth catalyst for the semiconductor industry. Logic is expected to remain another major contributor, growing 37 percent in 2026.

Other product categories are forecast to expand at more moderate rates, reflecting a broader industry growth: Microprocessors 20 percent, Analog 10 percent, Discrete Semiconductors 8 percent, Sensors and Optoelectronics with 3 percent.

Regionally, all major markets are projected to show strong growth. The Americas are expected to more than double in 2026 with 112 percent growth, driven by the concentration of AI-related semiconductor demand and cloud infrastructure investments. Asia Pacific is forecast to grow 87 percent, while Europe and Japan are projected to grow 58 percent and 28 percent respectively.

2027 Outlook: Growth Continues Above Historical Industry Trends

For 2027, WSTS forecasts the global semiconductor market to grow a further 27 percent, reaching approximately USD 1.9 trillion.

Memory is again expected to lead market expansion with projected growth of 32 percent, while Logic is forecast to increase by 27 percent. Continued deployment of AI systems, advanced computing infrastructure, and expanding semiconductor content across end markets are expected to support ongoing industry momentum.

All geographic regions are projected to continue growing in 2027, led by the Americas and Asia Pacific.

WSTS Forecast Summary

Shannon Davis

[BeenRetired] Omdia: OLED Display Demand for Notebook PCs to Reach $11.5B by 2033 Shannon Davi...

BeenRetired — 6/14/2026 11:29:54 AM

Omdia: OLED Display Demand for Notebook PCs to Reach $11.5B by 2033
Shannon Davis
1 week ago

New research from Omdia finds that OLED display shipments for notebook PCs is expected to grow to $11.5 billion by 2033, accounting for approximately 16.2% of total OLED display revenue.

OLED display revenue for notebook PC is expected to reach $4 billion in 2026, primarily driven by demand for Apple’s MacBook Pro series. From July 2026, Samsung Display will supply OLED panels for Apple MacBook Pro series (14.3-inch and 16.3-inch), with the devices expected to launch in 3Q 2026.

“Apple is adopting hybrid OLED for the MacBook Pro series based on oxide TFT and RGB tandem OLED technology,” said Jerry Kang, Practice Leader at Omdia. “This combination is being used for the first time in this form factor and is designed to reduce power consumption compared to LTPO and RGB single OLEDs.”

Over the past decade, most OLED displays for notebook PC have been based on the rigid OLED technology, similar to that used in mid-range smartphone OLEDs. However, anticipating rising demand for OLEDs in IT applications, such as tablets and notebook PCs, panel suppliers investing in Gen8.6 production capacity using a range of technologies, including LTPO and Oxide TFT-based processes.

In addition, manufacturers are exploring new patterning methods to improve efficiency in large-screen OLED production, such as Ink-Jet Printing (IJP) and Fine Photo-lithographic Mask (FPM), alongside the established Fine Metal Mask (FMM) method.

“As seen previously in the smartphone OLED display market, a variety of technology combinations including backplanes, substrates, and OLED patterning methods, will be applied to notebook PC OLED displays over the long term,” Kang said. “In particular, demand for hybrid OLED is expected to increase significantly for notebook PCs by 2033, as it enables thinner and lighter device designs by saving space for circuits and batteries.”

Omdia forecasts that the shipment share of hybrid OLED will increase from 12.6% in 2026 to 89.5% in 2033 for notebook PC demand.

This press release is based on Omdia’s “ OLED & Flexible Display Intelligence Service“. This report covers OLED trends, including application demand, industry issues, panel suppliers’ strategies, manufacturing technologies, supply/demand, and cost analysis.

PS
AMOLED + EUV/ArFi Thingy = beautiful wallet opening thing.

[BeenRetired] Quantum Diamond Magnetic Imaging for Non-Destructive Electrical Fault Localizati...

BeenRetired — 6/14/2026 11:18:34 AM

Quantum Diamond Magnetic Imaging for Non-Destructive Electrical Fault Localization
Pete Singer
1 week ago

By Fleming Bruckmaier, Co-founder and CTO, QuantumDiamonds GmbH.

Advanced 2.5D and 3D chip packages have created an inspection problem that existing failure analysis tools cannot fully solve. Lock-in thermography requires heat dissipation to generate a signal, rendering it insensitive to low-resistance defects and nearly blind to faults buried more than tens of microns below the surface. X-ray CT resolves structural geometry but cannot identify electrically active defects — voids in TSVs, leakage paths, latch-ups — that leave no structural signature. And X-ray imaging can irreparably damage high-bandwidth memory during analysis. Quantum diamond microscopy (QDM) addresses this gap by imaging the magnetic field generated by current flow itself, revealing where current is, where it isn’t, and where it flows in the wrong direction — without requiring heat dissipation, sample preparation, vacuum, or cryogenics.

The technology is based on nitrogen-vacancy (NV) centers in synthetic diamond — point defects whose electronic spin states are sensitive to external magnetic fields via the Zeeman effect. A widefield QDM instrument places a diamond sensor chip directly on the device under test. Green laser illumination initializes the spin state; spin-dependent photoluminescence provides optical readout after microwave manipulation. The result is a full magnetic field map with micrometer lateral resolution across a field of view spanning millimeters, acquired in minutes. Current path reconstruction via the Biot-Savart inverse problem yields a 3D current density map of the layer stack — directly revealing opens, partial opens, shorts, backside power delivery network defects, and current crowding in wide bandgap power devices.

QuantumDiamonds has commercialized QDM as the QD m.1, now deployed at leading failure analysis laboratories in Europe and the United States including EAG Laboratories in San Jose. Nine of the world’s ten largest chipmakers have engaged with the technology. The product roadmap targets InLine wafer mapping for 100% in-line screening by 2028 — positioning QDM not merely as a failure analysis tool but as yield management infrastructure for the advanced packaging era, where buried defects are the industry’s most common yield-killing failure mode and faster root cause identification translates directly into yield ramp acceleration.

Click here to read the full article in Semiconductor Digest magazine.

[BeenRetired] Seeing the Unseen: How Advanced X-ray Technology is Safeguarding Semiconductor R...

BeenRetired — 6/14/2026 11:14:18 AM

Seeing the Unseen: How Advanced X-ray Technology is Safeguarding Semiconductor Reliability
Pete Singer
1 week ago

By Christopher Rand, Principal Technical Engineer, Nordson Test and Inspection.

As semiconductor devices shrink and connection density grows, the economic argument for early defect detection becomes compelling: the further a defect propagates through manufacturing, the more expensive it becomes — potentially tens of thousands of dollars per device by the time a fully assembled package fails. X-ray inspection, which can identify structural defects non-destructively throughout the production process, is essential for applications in aerospace, automotive safety, and medical devices where failure in the field is not an option. At the heart of modern X-ray inspection is the sealed transmissive tube, which uses a crystal filament to produce a fine, efficient electron beam with high resolution, long operating lifetime, and consistent output — enabling the magnification and stability critical for inspecting micron-scale semiconductor structures.

X-ray’s effectiveness is amplified when combined with complementary techniques. Acoustic inspection excels at detecting delamination within silicon wafers — where X-ray struggles with contrast — while X-ray excels where acoustic signal recovery is obstructed by voids or complex geometry. Two-dimensional X-ray imaging is well-suited to high-volume production screening; three-dimensional computed tomography (CT) generates virtual cross-sections that can be analyzed repeatedly without destroying the sample, exponentially increasing detectability in complex chiplets, interposers, and heterogeneous die stacks. While 3D CT requires more time than single 2D passes, its ability to isolate individual layers makes it indispensable for failure analysis of highly complex devices.

The challenge is most acute for 3D chip stacking and heterogeneous flip-chip designs, where the density of connections and complexity of material stacks pushes single-technique inspection to its limits. A multi-technique, multi-stage strategy — 2D imaging for fast early-stage screening, 3D CT for complex structure analysis, acoustic inspection for specific delamination failure modes — matches detection capability to device complexity at each production stage. Identifying defects early, before successive processing layers obscure failure sites and accumulate additional value, is both more cost-effective and more reliable than relying on end-of-line testing alone.

Click here to read the full article in Semiconductor Digest magazine.

PS
I'm sticking with ASML and Village.

[BeenRetired] 1Q26 record WFE spend...on Leading-Edge & Packaging. SEMI Reports Global Se...

BeenRetired — 6/14/2026 11:06:15 AM

1Q26 record WFE spend...on Leading-Edge & Packaging.

SEMI Reports Global Semiconductor Equipment Billings Increased 14% Year-Over-Year in Q1 2026
Shannon Davis
1 week ago

SEMI, the industry association serving the global semiconductor and electronics design and manufacturing supply chain, today announced in its Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report that global semiconductor equipment billings increased 14% year-over-year to US$36.55 billion in the first quarter of 2026. First quarter 2026 billings registered a 1% quarter-over-quarter growth.

Record quarterly billings were driven by continued AI-related investment, including capacity expansion and technology upgrades supporting leading–edge logic, DRAM, and advanced packaging.

“The strong start to 2026 reflects continued industry investment in the capacity and infrastructure needed to support AI-driven semiconductor growth,” said Ajit Manocha, SEMI President and CEO. “Record first-quarter billings highlight ongoing momentum in leading-edge manufacturing and advanced packaging.

Compiled from data submitted by members of SEMI and the Semiconductor Equipment Association of Japan (SEAJ), the WWSEMS report is a summary of the monthly billings figures for the global semiconductor equipment industry.

The following are quarterly billings data in billions of U.S. dollars, with quarter-over-quarter and year-over-year changes by region:

[BeenRetired] "ASML demonstrate 1,000-watt EUV...reduce steps from 100 to 10" "ASML demonstra...

BeenRetired — 6/14/2026 10:52:47 AM

"ASML demonstrate 1,000-watt EUV...reduce steps from 100 to 10"

"ASML demonstrated a 1,000-watt EUV source, pushed High NA capability that can "reduce the number of process steps from 100 to 10," and lifted the NXE:3800F roadmap to 260 wafers per hour. The gap between these competitors is widening.

The competitive threat that never was: ASML’s widening moat boosts stock 77% YTD

Copilot:

Short answer: The latest public shipping status for the NXE:3800F is that ASML has not yet begun volume shipments, but the tool’s specification has been officially raised to 260 wafers per hour, and it is positioned as the next-generation Low-NA EUV system following the NXE:3800E. All current information comes from ASML’s Q1 2026 earnings disclosures, which explicitly discuss the 3800F’s roadmap but do not report customer shipments yet.

What’s actually confirmed about NXE:3800F (as of Q1 2026)1. Throughput target raised to 260 wphASML increased the official spec from 250 ? 260 wafers/hour.

This is part of the same disclosure that also confirmed the 1,000-watt EUV source demonstration.

2. No public evidence of customer shipments yet
Across all Q1 2026 reporting, ASML discusses:

NXE:3800E upgrades (220 ? 230 wph)
NXE:3800F spec uplift (250 ? 260 wph)
High-NA EXE progress
2026–2027 EUV unit capacity plans

…but does not list any NXE:3800F shipments.

ASML typically announces first-in-fab milestones for new EUV platforms (e.g., 3400C, 3600D, 3800E), and no such milestone has been reported for the 3800F.

3. 3800F is part of the 2027+ Low-NA capacity ramp
ASML’s guidance shows:

60+ Low-NA EUV units in 2026
80+ Low-NA EUV units in 2027

The 3800F is implicitly included in this roadmap, but not yet shipping.

4. 1,000-watt source demonstration extends Low-NA roadmap to 330 wph
This is the same context in which the 3800F spec uplift was announced.

This is important because the 3800F is the first Low-NA platform expected to absorb the higher-power source.

Bottom line

NXE:3800F is not shipping yet (no customer deliveries reported).
Spec uplift to 260 wph is official.
Roadmap aligns with 2027 volume Low-NA EUV expansion.
1,000-watt source demo confirms long-term scaling path.

If you want, I can also map:

Where 3800F fits vs 3800E and EXE:5200
Which fabs are most likely first recipients (TSMC, Intel, Samsung)
How 260 wph + 1 kW source changes cost per layer and fab economics

PS
Shrink n Stack n Package bonanza JUST started...as EUV ramps to supply it.

[BeenRetired] Beating AI Bottlenecks with Better Switches Pete Singer 1 week ago AI’s infrast...

BeenRetired — 6/14/2026 10:26:45 AM

Beating AI Bottlenecks with Better Switches
Pete Singer
1 week ago

AI’s infrastructure demands extend well beyond compute: chips must be tested before they ship, and semiconductor test equipment for AI chips faces compounding challenges. AI chips have extremely dense pinouts, 2.5D and 3D integration technologies like high-bandwidth memory stacks restrict probe access, and tester circuitry must operate at or above the speed of the fastest signal on any die it encounters. Corporate AI investment reached $252.3 billion in 2024, up 25.5% year-over-year. In this environment, the switch matrices that route signals between test instruments and device pins have emerged as a meaningful production bottleneck.

Traditional automatic test equipment uses crosspoint relay matrices — often implemented with reed relays — to connect instruments to device pins. Reed relays have measurable actuation and settling times, and armature vibration after contact introduces noise into measurements. These delays accumulate across high-volume AI chip test programs, extending cycle times and slowing production throughput. Menlo Micro’s MEMS-based relays, fabricated using semiconductor production techniques, offer near-ideal switching characteristics: essentially zero on-resistance, infinite off-resistance, sub-microsecond switching and settling times, and no armature vibration. Their small footprint supports the functional density that modern IC testers require, and they can scale testing speed, density, and reliability simultaneously.

The transition to MEMS relays removes a structural constraint rather than offering incremental improvement. By enabling almost instantaneous signal routing with negligible interference, MEMS-based switch matrices ensure that production testing keeps pace with AI chip evolution rather than becoming a choke point limiting how quickly advanced models reach deployment. As AI chip complexity and pin density continue to increase with each generation, test infrastructure that can match that evolution in speed and reliability becomes an essential enabling technology — not an optional upgrade to consider later.

Click here to read the full article in Semiconductor Digest magazine.

[BeenRetired] Covalent Expands Wafer-Level Semiconductor Characterization Through Oxford Instr...

BeenRetired — 6/14/2026 10:21:56 AM

Covalent Expands Wafer-Level Semiconductor Characterization Through Oxford Instruments Collaboration
Shannon Davis
6 days ago

Covalent today announced a strategic collaboration with Oxford Instruments that expands its semiconductor characterization offering with customer-ready, wafer-level Raman and photoluminescence (PL) workflows. The capability is now available to customers tackling defectivity, stress and strain mapping, process development, and failure analysis at full-wafer scale.

As materials such as silicon carbide (SiC) and gallium nitride (GaN) move into high-volume production, teams increasingly need non-destructive, spatially resolved insight across entire wafers. Historically, these measurements have been limited in throughput, accessibility, or scale. Covalent’s integrated workflows now make it faster and more practical to generate high-resolution Raman and PL data across wafers up to 300 mm, enabling customers to identify defects earlier, correlate material properties, and accelerate development cycles.

Through the collaboration, Covalent has incorporated Oxford Instruments WITec360 Raman technology into its application-driven environment, configuring the system with dual 355 nm and 532 nm laser excitation. This approach enables complementary surface-sensitive PL analysis alongside high-resolution Raman imaging within a unified workflow, supporting a broader range of compound semiconductor and advanced materials challenges.

For customers, the impact is practical: faster root-cause analysis, more reliable process monitoring, and improved confidence in scaling new materials and devices. Wafer-level mapping of crystallinity, doping, stress, and defects can now be performed in a single, integrated workflow designed around real production and R&D needs rather than standalone instrumentation.

“This is about expanding what our customers can do, not just what we can measure,” said Craig Hunter, CEO of Covalent. “We’ve taken Oxford Instruments’ powerful Raman technology and built it into workflows that directly support yield improvement, process control, and failure analysis at wafer scale.”

Oxford Instruments’ role is foundational to enabling this capability. “Our Raman platforms are built to provide fast, high-resolution, non-destructive insight into complex semiconductor materials on wafer sizes up to 300mm. By partnering with Covalent, we’re helping customers to bridge the gap from R&D to high-volume production, accelerating both development and manufacturing outcomes,” said Vahan Tchakerian, Senior Vice President of Sales & Applications at Oxford Instruments.

By combining Oxford’s Raman platform with Covalent’s material characterization expertise and application development, customers now have access to a more scalable and commercially useful approach to wafer-level analysis.

[BeenRetired] AWS, Azure & Google Cloud "are crushing it" The rolling MoAPS happening everywh...

BeenRetired — 6/14/2026 10:20:02 AM

AWS, Azure & Google Cloud "are crushing it"

The rolling MoAPS happening everywher

The established companies are crushing it
AWS is the largest cloud infrastructure operation in the world, and actually provides most of Amazon's profits. AWS accounted for 59% of Amazon's operating income in Q1, and its revenue grew at a 28% rate -- its fastest expansion in nearly four years.

Microsoft doesn't divulge as much information about Azure as AWS and Google Cloud do. It only provides the business unit's growth rate, which was still an impressive 40% in its latest quarter.

However, Google Cloud tops both of them, with an impressive 63% growth rate, but it had some help from its Tensor Processing Units (TPUs).

TPUs are powerful computing units that can outperform general-purpose GPUs from a cost standpoint when handling the specific deep learning and matrix mathematics workloads they are designed for. Deploying its TPUs helped Alphabet catch up in the AI build-out, and now, it is starting to sell those proprietary AI chips directly to other companies rather than just renting out their processing power. With external sales of these units contributing to Google Cloud's growth rate, the waters get a bit murky in terms of gauging how well the infrastructure business alone is doing, but it's still the fastest-growing of the three despite being the smallest.

While Microsoft doesn't provide exact profitability information, I think it's safe to assume that Azure is producing a ton of profits for Microsoft. With all three legacy players making a ton of money from their cloud computing divisions, that means cloud computing can be a viable standalone business. But can CoreWeave and Nebius get to that point?

Rapid growth, but no profits
CoreWeave and Nebius are both neocloud companies -- cloud computing specialists that are focused on AI. The two have differing business models, but each has attracted major tech players including Microsoft and Meta Platforms as clients. These customers already have data centers of their own, but being able to rapidly obtain more of the computing power they need without having to build it is still an option they find valuable.

Demand from those customers and others is giving CoreWeave and Nebius jaw-dropping growth rates compared to the legacy cloud companies. In Q1, CoreWeave's revenue grew by 112% year over year while Nebius' soared by 684%.

Meet the 2 newcomers challenging the cloud computing titans in artificial intelligence (AI)

[BeenRetired] 18A for Firefly Wildcat Lake. Up to 64GB LPDDR5X. Amazing, until today, for budg...

BeenRetired — 6/14/2026 9:55:20 AM

18A for Firefly Wildcat Lake. Up to 64GB LPDDR5X.
Amazing, until today, for budget PC.
Only possible with ASML tools.

Digital Trends

Intel details Project Firefly and how it’s pushing affordable laptops to unseat the MacBook Neo
Story by Rachit Agarwal
Jun 13 • 2 min read • Updated 6h ago

Key takeaways

Affordable Performance: Project Firefly centers on Wildcat Lake, a custom chip with 2 P-cores for speed, 4 LP E-cores for battery life, a small NPU, and capable graphics for 720p video and light gaming.
Reference Design Ecosystem: Intel provides laptop makers with a ready-made design, including chassis, screen, and integrated phone-derived components to cut costs and simplify production.
Challenging Premium Laptops: While not directly targeting Apple, Firefly aims to deliver a premium-like experience at budget prices, inspired by the success of the MacBook Neo.

It’s no secret that the Windows budget-market segment has been stagnating for years. While premium machines kept getting thinner, lighter, and faster, the affordable segment was stuck with five to seven year old technology and minor updates.

Intel, it seems, wants to change that. In a recent Talking Tech interview, the company detailed how Project Firefly plans to drastically overhaul the budget laptop segment by creating a whole new ecosystem of laptops.

What exactly is Project Firefly?At the heart of the project is Wildcat Lake, a chip Intel custom-built for everyday users. It packs two P-cores for snappy performance and four LP E-cores for longer battery life, along with a small NPU and right-sized graphics that can handle smooth video playback and light gaming at 720p. Intel also went with a single-tile design and a cheaper six-layer motherboard to keep costs in check.

Intel

But a chip alone doesn’t make a laptop, and that’s where Firefly is different. It’s a reference design program that hands laptop makers a ready-made recipe, complete with the right chassis, screen, and form factor. The prototype Intel showed off is just 12.9mm thin, features a sturdy metal body , and comes in a lovely lavender color that the company calls its Intel color.

Instead of using the usual PC components, Intel raided the phone world, borrowing memory and audio chips from an ecosystem that’s far bigger and cheaper than the PC one. It even bundled its chip and phone memory into one neat package that laptop makers can pop straight into their designs, saving them a ton of time and effort.

Can it take on the MacBook Neo?Intel never names Apple’s budget MacBook directly, and in the interview, the company insisted Firefly isn’t a response to any particular competitor. That said, Intel openly admitted it admires what Apple has built and wants to bring similar experiences to the broadest user base possible.

While Intel won’t say it out loud, the message is hidden in the subtext. It took the launch of MacBook Neo to wake up Windows manufacturers and push them to start taking the mainstream market more seriously, and for this reason alone, MacBook Neo has served its purpose.

And if Firefly delivers, you won’t have to spend premium money to get a laptop that feels premium, and that’s a win for all of us.

Copilot:
Process Node

Intel 18A (bleeding-edge node, unusually high-end for a budget chip)

Graphics
Two different descriptions appear depending on the SKU class:

Firefly-class Wildcat Lake (Core Series 3)

2-core Xe3 GPU (very small, optimized for 720p and streaming)

Higher-end Wildcat Lake variants (not Firefly-specific)

Xe-LP GPU with up to 32 EUs

This discrepancy is because:

Firefly uses the lowest-cost Wildcat Lake silicon (2 Xe3 cores).
Higher SKUs in the Wildcat Lake family use a larger GPU block.

NPU

Tiny 1-tile NPU (Firefly-class)

Higher-end Wildcat Lake SKUs can reach 40 TOPS, but Firefly’s chip is the minimal configuration.

Memory Support

LPDDR5X (phone-class memory)
Up to 64 GB
Single-channel layout (to reduce board area and cost)

Notebookcheck also confirms that Firefly laptops can use smartphone-grade DRAM.

[BeenRetired] Cadence deal with Intel backs bullish thesis on Cadence’s agentic AI [graphic] B...

BeenRetired — 6/14/2026 9:17:17 AM

Cadence deal with Intel backs bullish thesis on Cadence’s agentic AI

Barchart

Cadence deal with Intel backs bullish thesis on Cadence’s agentic AI
Story by Larry Ramer
Jun 13 • 3 min read • Updated 19h ago

Cadence (CDNS) recently announced that it had expanded its collaboration with Intel's (INTC) chip-manufacturing unit, known as Intel Foundry. Under the deal, Intel will utilize Cadence's AI agents and its Design IP products to enhance “Intel’s next-generation process technologies, beginning with Intel 14A.” The agreement provides evidence that my previous, bullish thesis on Cadence is valid and, together with Cadence's impressive first-quarter results and analysts' bullish view on the shares, makes CDNS stock a buy for growth investors.

About Cadence Design Systems
The company specializes in developing various verification, simulation, and design software and platforms. Based in San Jose, California, Cadence is changing hands with a market capitalization of $107.8 billion and a forward price-to-earnings (P/E) ratio of 63.3x.

In the three months that ended on the early morning of June 10, the shares had advanced 31%, while they had risen 23% in 2026.

Cadence's AI Agent Appears to Be a Game Changer
In a previous column, I explained that Cadence's AI agent “allows AI chips to be created much more quickly and easily” and “autonomously creates and verifies designs.” I asserted that the product would be a positive game changer because it would "allow chipmakers to meaningfully reduce their costs and raise their profits."

Intel's decision to utilize CDNS' agent suggests that the product is indeed very useful for chipmakers and is likely to significantly move the needle for Cadence's financial results and CDNS stock over the longer term.

Although Stifel, an investment bank, is not as enthusiastic as I am about the agreement, it did call the deal “incrementally positive” for Cadence for a number of reasons. Specifically, Stifel thinks that the partnership provides “validation” of Cadence's agentic AI, will enable Cadence to benefit to a greater extent from the potential growth of Intel Foundry, and looks poised to boost Cadence's longer-term revenue outlook.

The investment bank increased its price target on the shares to $432 from $395 and kept a “Buy” rating on the name.

Cadence Reported Strong Q1 Results
Last quarter, the firm's revenue jumped to $1.47 billion, versus $1.24 billion during the same period a year earlier, while its earnings per share climbed to $1.23, versus $1 in Q1 of 2025. Further, CDNS expects its top line to increase by a robust 17% in 2026, and its backlog rose to a record $8 billion.

“Cadence had a strong start to 2026, delivering a solid Q1 with accelerating AI demand and record backlog, reflecting strong customer commitment to our AI-driven portfolio,” CEO Anirudh Devgan said in a statement. The CEO added that “Cadence is leading the agentic AI transformation in semiconductor and system design.”

Analysts Are Upbeat on CDNS Stock
Analysts on average, and have for at least the last three months, viewed CDNS stock as a “Strong Buy,” with 18 of 23 analysts giving it a “Strong Buy” rating.

In addition to Stifel, Citi is also bullish on the name. Following the company's Q1 results, the latter bank raised its price target on the shares to $400 from $385 and kept a “Buy” rating on the stock.

PS
Frenetic Shrink n Stack n Package pace can ONLY speed up.
SVG/Cymer/Brion/HMI/Mapper/Berliner Glas/ASML/et al owns the tools it produces...includes Metrology & Inspection not just EUV, ArFi, ArF, KrF Litho.
It's JUST started.
:-)

[BeenRetired] "From ASML's perspective, though, Oracle's bad news could be quite good" [grap...

BeenRetired — 6/13/2026 1:00:38 PM

"From ASML's perspective, though, Oracle's bad news could be quite good"

The Motley Fool

Why ASML Holding stock popped today
Story by Rich Smith
Jun 11 • 3 min read • Updated 1d ago

Key takeaways

Earnings Boost: Oracle beat earnings expectations, reporting $2.11 per share on $19.2B revenue, sparking optimism for ASML.
AI Investment Impact: Oracle plans to raise $20B more to fund AI data centers, which means higher demand for AI chips and ASML’s manufacturing equipment.
Stock Outlook: ASML could see 23% earnings growth over the next five years, though Motley Fool suggests other stocks may offer better returns.

Key Points

Oracle beat earnings last night, but also announced plans to raise another $20 billion in cash.
Oracle needs cash to build AI data centers full of AI chips.
ASML makes the machines that manufacturer those chips.
10 stocks we like better than ASML ›

ASML (NASDAQ: ASML) shares gained 5.2% through 11:40 a.m. ET Thursday, and investors can thank Oracle (NYSE: ORCL) for the good news.

Oracle "beat" on earnings last night, earning $2.11 per share on $19.2 billion in quarterly sales -- both numbers higher than analysts had expected. More important to ASML investors, though, is what Oracle revealed about its plans.

What Oracle is up to in AI
Specifically, Oracle said it must raise another $20 billion through debt issuances and share sales. This is on top of $20 billion in share sales already announced... and $48 billion raised last year.

From Oracle's perspective, these cash raises are necessary to offset the $23.7 billion in cash the company is burning annually as it builds out data centers to support its hundreds of billions of dollars' worth of long-term contracts to supply artificial intelligence support to its AI clients -- a major worry for investors in Oracle stock.

What this means for ASML stock
From ASML's perspective, though, Oracle's bad news could be quite good. If Oracle is raising tens of billions of dollars, this logically means Oracle is also planning to spend tens of billions of dollars on AI chips for its data centers. As this money flows to Oracle's chip suppliers, it's furthermore logical to assume these chipmakers will turn around and spend much of this money on AI chip manufacturing equipment from ASML.

Long story short, the more Oracle spends, the more revenue and profit ASML can expect to collect -- and Oracle just told us it intends to spend quite a lot of money. This bodes well for ASML's chances of hitting analyst targets for 23% earnings growth over the next five years -- and that's a good reason for ASML stock going up today.

[BeenRetired] Invisix Raises €20M Seed Round to Bring Soft X-Ray Metrology to AI-Era Chip Manu...

BeenRetired — 6/13/2026 12:29:13 PM

Invisix Raises €20M Seed Round to Bring Soft X-Ray Metrology to AI-Era Chip Manufacturing
Shannon Davis
2 weeks ago

Invisix, the semiconductor metrology company developing next-generation measurement tools for advanced chip manufacturing, has raised an oversubscribed €20 million seed round, which includes Hitachi Ventures, Transition Ventures, imec.xpand, Doosan Investment Co., and a tier-1 semiconductor manufacturer. The funding will be used to grow the Invisix team, accelerate development of its first shippable system, and support customer demonstrations at a new cleanroom in Eindhoven.

Helping chipmakers build what they can’t yet see

Building a modern chip is like building a nanoscale skyscraper: before adding the next layer, manufacturers need to know if the previous one printed correctly. Yet as advanced logic and memory devices become ever smaller and more complex, optical tools can no longer resolve the internal structures that matter most.

These devices form the backbone of high-performance computing and underpin the promise of AI. Without the ability to measure them, manufacturers are forced into slower, costlier, often destructive alternatives. In a market where even marginal yield improvements can unlock billions in revenue and dominance is won by bringing new nodes into production ahead of competitors, that gap is critical.

Founded by ASML alumni and PhD physicists CEO Christina Porter and CTO Sietse van der Post, Invisix solves this with a soft x-ray metrology system designed to help chipmakers measure the most challenging layers at scale.

A non-destructive, high-throughput solution

Invisix’s system sees beyond existing measurement tools by using High Harmonic Generation (HHG), a process rooted in discoveries recognised by the 2023 Nobel Prize in Physics. HHG uses a short-pulsed drive laser to excite noble-gas atoms into a high-energy state. In this state, the atoms emit short-wavelength light, known as soft x-rays, at many colours, generating a richer 3D signal than typical single-wavelength lasers.

Invisix’s system combines HHG with proprietary reconstruction algorithms and machine learning to reconstruct the detailed 3D internal structure of devices. It crucially achieves this in a non-destructive way, and the whole system’s architecture has been designed to scale to the throughput needed for high-volume manufacturing.

Built on more than a decade of ASML technology development

Invisix applies to metrology the same resolution logic that transformed semiconductor lithography. As chip features shrink, measurement wavelengths must shrink too. The company uses soft x-rays to see inside the buried nanoscale structures that optical tools can no longer resolve.

The company has licensed a substantial technology package from work on soft x-ray performed at ASML. The founders are joined by many veterans of the ASML soft x-ray program, as well as senior industry hires including COO Roald Dogge, formerly COO of NTS, a major Dutch semiconductor contract manufacturer. Invisix’s research lineage also extends to a long-standing collaboration with Professor Anne L’Huillier of Lund University, who was awarded the Nobel Prize for her foundational work on the physics behind HHG.

The Invisix team already publicly demonstrated its technology in 2023, disclosing results in collaboration with Intel and imec. They successfully measured key features in next-generation gate-all-around transistor architectures, one of the most challenging targets for existing metrology. The company recently relocated its 300mm-wafer-capable soft x-ray testbench to a new cleanroom in Eindhoven, where customer demonstrations will continue in parallel with development of its first shippable product for deployment in customer fabs.

Christina Porter, PhD, co-founder and CEO of Invisix, said: “Semiconductor manufacturers can’t build what they can’t see. As chips become more 3D, the industry needs a new generation of metrology tools that can look inside these incredibly complex miniature skyscrapers without destroying them. We are entering the market with technology that has been incubated inside ASML for more than a decade — a level of technical de-risking that is unusual for a seed-stage hardware company and gives our customers a faster path to deployment.”

Wolfgang Seibold, Partner & Chief Investment Officer at Hitachi Ventures, said: “As semiconductor architectures grow more three-dimensional, metrology increasingly limits semiconductor yield and ramp speed, with each new node generation intensifying the challenge. Invisix tackles this with a technology platform backed by a decade of ASML development, proven results with leading industry partners, and a system architecture designed for high-volume manufacturing. We’re excited to support the team as they bring this capability to the market.”

Clara Ricard, Partner at Transition Ventures, said: “It’s exciting to see world-class talent come out of ASML and build companies of their own. Invisix is one of Europe’s most promising semiconductor companies: they unlock a major bottleneck for manufacturing advanced chips that power AI training and inference. The technology is de-risked, the market is moving fast, and we’re thrilled to back them as they scale.”

[BeenRetired] CEA-Leti Presents Die-to-Wafer Hybrid Bonding At 1 µm Pitch Shannon Davis 2 week...

BeenRetired — 6/13/2026 12:23:49 PM

CEA-Leti Presents Die-to-Wafer Hybrid Bonding At 1 µm Pitch
Shannon Davis
2 weeks ago

CEA-Leti today announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1 µm. The findings were presented at the Electronic Components and Technology Conference (ECTC) 2026.

As Moore’s Law reaches physical limits---Huh?---, the semiconductor industry is increasingly relying on 3D stacking to enhance performance and energy efficiency. This D2W technology addresses a critical bottleneck in AI accelerator design: interconnect density and bandwidth. By vertically stacking device layers with ultra-fine pitches, the technology shortens interconnect paths, significantly increasing data transfer speeds while reducing power consumption.

“This successful electrical testing of structures with up to 100,000 links confirms the viability of this technology for high-density interconnects,” said Melissa Najem, CEA-Leti research engineer and lead author of the paper, “Die-to-Wafer Hybrid Bonding Technology Down to 1 µm Pitch for Multi-Die Stacking Integration.”

“Combining multi-fine pitch D2W with inter-die gap filling, high-density through-silicon vias, and through-oxide vias paves the route toward multi-die stacking. These developments represent a vital step toward overcoming the physical limitations of current semiconductor scaling, enabling more compact, powerful, and energy-efficient electronic systems,” she added. “This 1-µm fine-pitch Cu-Cu interconnect in D2W is a world first, to the best of our knowledge.”

Overcoming Alignment and Planarization Challenges

Achieving a 1 µm pitch required the team to engineer very precise alignment accuracy, the primary challenge for the D2W building block. Additionally, the wafer reconstruction process involving inter-die gap filling (IDGF) demanded optimized chemical mechanical planarization (CMP) to ensure compatibility with subsequent vertical interconnects.

Electrical characterization of daisy-chain structures confirmed expected performance and yields for pitches ranging from 5 µm down to 2 µm. While the yield at 1 µm is limited by the alignment accuracy of existing bonding tools, the team anticipates significant improvements with the introduction of next-generation tools featuring 0.5 µm (3s) alignment capabilities.

Roadmap to 0.5 µm Pitch and Beyond

This demonstration serves as a transitional proof of concept, laying the groundwork for a second-generation test vehicle. The immediate next steps include integrating the D2W technology with vertical interconnections—specifically high density through-silicon vias (HD TSV) and through-oxide vias (TOV)—facilitated by the intermediate inter-die gap filling (IDGF) process step.

“In the future, we will target a D2W hybrid-bonding test vehicle with a pitch of 0.5 µm to further improve interconnect density for advanced AI applications,” explained Jean-Charles Souriau, scientific director at CEA-Leti. “This advancement aims to cater to the escalating demands of next-generation AI accelerators and CMOS image sensors.”

Roadmap to Multi-die Stacking Architectures

The building blocks related to IDGF, TOV and HD TSV will enable the integration of different dies and functions with dense vertical interconnections.

“These technologies enable advanced wafer reconstruction and complex multi-die stacking for innovative architectures. Moreover, the combination of D2W and W2W technologies is of high interest to address both performance and cost requirements for future digital devices and systems,” said Eric Ollier, director of the Smart Imager and Advanced Smart Vision programs at IRT Nanoelec.

The D2W research was carried out within the framework of the FAMES Pilot Line and the ANR NextGen project (France 2030 initiative). Related IDGF, TOV and HD TSV studies were supported by IRT Nanoelec.

A CEA-Leti team has focused for more than 15 years on the key enabling technology of hybrid bonding (W2W and D2W) and HD TSV for the three-layer CMOS image sensors under development at IRT Nanoelec, and it publishes several papers at every ECTC conference. The institute received a highlighted-paper recognition at ECTC 2024 for demonstrating a three-layer test vehicle that featured two embedded Cu-Cu hybrid-bonding interfaces, face-to-face (F2F) and face-to-back (F2B), and one wafer containing HD TSVs.

[BeenRetired] New Report Finds Semiconductors Account for 95% of an AI Data Server Rack’s Valu...

BeenRetired — 6/13/2026 11:54:15 AM

New Report Finds Semiconductors Account for 95% of an AI Data Server Rack’s Value, Encompassing the Full Stack of Chip Technologies
Shannon Davis
2 weeks ago

he Semiconductor Industry Association (SIA), in partnership with Deloitte, today released a report finding the full range of semiconductor technologies are integral to artificial intelligence (AI), accounting for a significant share of the value of AI infrastructure and presenting a massive market opportunity in the years ahead.

The report, titled “ Powering AI: The Semiconductor Ecosystem at the Foundation of Data Centers,” offers a unique, inside-out look at the heart of AI infrastructure by conducting a virtual teardown of a state-of-the-art AI data server rack, the foundational unit of centralized AI infrastructure.

As policymakers advance efforts to promote U.S. leadership in AI – including the Trump Administration’s Pax Silica Initiative and its AI Exports Program – the new report finds chips account for more than 95% of a leading AI server rack’s content value and more than 50% of the total capital expenditures required for building and operating an AI data center. The study also details how AI requires the full range of semiconductor technologies, including logic, memory, and analog and foundational chips. Additionally, the report projects annual revenue for semiconductors used in AI data centers could reach $1.2 trillion by 2028. This represents a nearly tenfold increase over the last four years and surpasses total global semiconductor sales from 2025 – across all end uses – by more than 50%.

“The future of AI will be determined by the full array of semiconductor technologies that power it,” said John Neuffer, SIA president and CEO. “To ensure global AI adoption is built on American chips, we need government policies that promote access to global markets and strengthen U.S. competitiveness. We stand ready to work with policymakers to ensure American semiconductor technology remains the engine of AI innovation for many years to come.”

[BeenRetired] TCO: ASML wheelhouse. Beyond PPA: How Total Cost of Ownership Is Reshaping ...

BeenRetired — 6/12/2026 1:14:16 PM

TCO: ASML wheelhouse.

Beyond PPA: How Total Cost of Ownership Is Reshaping Chip Design
Pete Singer
1 day ago

By Ken Dare, Q&A with Adarsh Mittal.

As semiconductor nodes advance to 3nm and below, mask sets cost tens of millions of dollars, yield ramps lengthen, and EUV complexity compounds — making the traditional metric of power, performance, and area (PPA) an insufficient guide for design decisions. Senior ASIC engineer Adarsh Mittal argues that total cost of ownership (TCO) must now be the dominant framework, encompassing cooling infrastructure, software tuning overhead, operational complexity, and long-term reliability alongside silicon metrics. A 10% performance gain that comes at the price of a 40% increase in wafer cost and doubled validation cycles is, by TCO standards, a bad trade.

TCO-aware design starts during microarchitecture, not after tape-out. Architects should model power density, thermal behavior, and infrastructure costs as first-class constraints — simulating worst-case and mixed-workload scenarios rather than optimizing for peak benchmarks. Key performance indicators like performance per watt under sustained production workloads, P99 latency stability, and incident rates provide a more realistic view of downstream cost and operational risk.

Leading companies like NVIDIA and AMD already measure success through performance per dollar, rack-level efficiency, and long-term operational expense rather than gigahertz or die size alone. Adopting TCO thinking strengthens cross-functional alignment, reveals hidden cost drivers like excessive mask spins and overdesigned performance margins, and ultimately enables chips that are commercially sustainable and strategically competitive — not just technically impressive at tape-out.

PS
EUV/ArFi Age ASML all tailwinds all the time.

[BeenRetired] "Vera CPU, could become available in the country as soon as August" Nvidia is t...

BeenRetired — 6/12/2026 12:23:21 PM

"Vera CPU, could become available in the country as soon as August"

Nvidia is telling Chinese customers it could be ready to sell them more advanced AI chips soon
Nvidia is telling Chinese customers it could be ready to sell them more advanced AI chips soon

Story by Aaron McDade • 1h

Key Takeaways

Nvidia has told Chinese customers its could be ready to sell more advanced AI chips in the country as soon as August, Reuters reported.
Nvidia, which has grappled with restrictions on exports of its most capable chips, has long been looking to boost its sales to China.

Nvidia could be getting closer to selling more of its AI chips in China.

Nvidia ( NVDA) has started telling customers in China that its next-generation AI chip, the Vera CPU, could become available in the country as soon as August, Reuters reported Friday. At least one Chinese company is planning an order of at least 300 servers with the new Vera chip to test the hardware before ordering more, according to the report.

Such a development would mark a major breakthrough for Nvidia, which has struggled to sell more of its AI chips to the country in the face of restrictions on exports of its most capable chips, and has long been looking to boost its sales to China.

Nvidia did not respond to an Investopedia request for comment on the report in time for publication.

Why This Matters to InvestorsNvidia executives have said that greater access to China's market could significantly boost sales, with CEO Jensen Huang previously telling investors that China's market could represent a $50 billion opportunity for the company annually.

Still, while around 10 Chinese companies have been approved by the U.S. government as customers for Nvidia's less advanced line of H200 chips, Reuters reported that none of those chips have actually been delivered, as the Chinese government has discouraged sales to boost domestic chipmakers. Last month, Nvidia told investors it had yet to record any revenue from sales of those chips to China.

Nvidia shares were little changed in recent trading. The AI chip leader's shares are up about 10% since the start of the year.

[BeenRetired] MediaTek doubles its AI chip target to $2 billion and enters the data center - S...

BeenRetired — 6/12/2026 5:55:38 AM

MediaTek doubles its AI chip target to $2 billion and enters the data center - Startup Fortune

MediaTek doubles its AI chip target to $2 billion and enters the data center
MediaTek has doubled its 2026 AI ASIC revenue target to $2 billion, anchored by a Google hyperscaler program and its co-designed N1X CPU inside Nvidia's RTX Spark AI PC chip. The company is targeting 10 to 15 percent of a $70 to $80 billion custom chip market by 2027, challenging Broadcom's long dominance, while investor rotation out of concentration-heavy TSMC positions has driven MediaTek shares up roughly 150% year-to-date.

Walter Schulze
Jun 11, 2026 · 4:47 PM·

MediaTek has doubled its 2026 AI chip revenue target to $2 billion and is gunning for hyperscaler custom silicon business that Broadcom has dominated for years, as investors rotate out of TSMC and into the Taiwanese chipmaker at a pace not seen in over a decade.

The numbers are hard to dismiss. MediaTek's stock has gained roughly 150% year-to-date, outperforming TSMC by the widest margin since 2009, and its April announcement doubling the 2026 AI ASIC revenue target from $1 billion to $2 billion landed with real force. But the more interesting question is not whether MediaTek has had a good year. It is whether the company, long identified as a budget-tier smartphone chip supplier trailing Qualcomm, has genuinely earned a seat at the table where Broadcom and Marvell have held court for years.

The primary evidence that it has: Google. MediaTek's first major AI accelerator program for a U.S. hyperscaler, widely understood to sit within Google's TPU development pipeline, is on schedule, with the company now targeting $2 billion in AI ASIC revenue for 2026. A second AI accelerator project is already in development, aimed at volume production by end-2027. At the company's 2026 analyst day, management described multi-year order visibility for its data center line and laid out a target of 10 to 15 percent of what it estimates will be a $70 to $80 billion AI ASIC total addressable market by 2027. That is not a roadmap slide. That is a commitment.

Broadcom's position in this market makes clear what MediaTek is actually up against. As CNBC's analysis of Broadcom's latest earnings made clear, the company reported $10.8 billion in AI semiconductor revenue in Q2 fiscal 2026 after posting $8.4 billion in the prior quarter, and together with Marvell controls an estimated 95% of the custom AI ASIC co-design market. Those relationships run deep. Broadcom has co-designed Google's TPUs for years and holds Meta's MTIA chips as another flagship program. More than brand loyalty, Broadcom and Marvell own the networking-to-compute interconnect fabric installed in many hyperscaler data centers, which means switching partners is not a simple procurement call. It is an architectural overhaul.

Still, Google is doing something deliberate. Reports suggest the company is introducing MediaTek into its supply chain not to replace Broadcom but to use it as competitive pressure on pricing. That is a real foothold. Even playing second fiddle in a Google program at $2 billion in annual revenue is a meaningful business, and Google's willingness to run parallel development tracks tells you something about how much leverage Broadcom currently enjoys in contract negotiations. MediaTek's cost structure, honed over years of competing in price-sensitive smartphone markets, may be precisely what hyperscalers want when they push into inference workloads that do not demand Broadcom's most sophisticated training silicon. Custom AI chip shipments are forecast to grow at triple the rate of GPU shipments in 2026, and the inference tier is where that growth concentrates.

The RTX Spark announcement at Computex 2026 reinforces MediaTek's credentials. Nvidia's new AI PC chip, unveiled June 1, pairs a Blackwell GPU with a MediaTek-linked Arm CPU design on a single TSMC 3nm system-on-chip, with 70 billion transistors, 6,144 CUDA cores, and up to 128GB of unified memory running at 300GB per second. Devices from Microsoft, Dell, HP, Lenovo, ASUS, and MSI are set to debut this fall. Having Nvidia lean on MediaTek's CPU and system-on-chip expertise for its first serious push into the Windows PC market is not an accidental endorsement. It means MediaTek is credentialed at the leading edge of silicon design, co-producing chips with the dominant AI hardware company on a platform targeting mass deployment.

The capital rotation behind the stock move
Bloomberg flagged in May that TSMC's weighting in global semiconductor indices and single-stock concentration limits at major funds has made continued accumulation structurally difficult. As AI enthusiasm has broadened beyond Nvidia and its foundry relationship with TSMC, concentration-limited funds are actively seeking other places to deploy capital in the semiconductor supply chain. MediaTek's share of that overflow is not purely speculative; the AI ASIC revenue ramp gives it fundamental support that many AI-adjacent stocks lack. That said, the 150% year-to-date gain already prices in substantial execution, and a Q1 2026 profit decline of 18% year-over-year is a reminder that the smartphone business, still the core of MediaTek's revenue, is under real pressure.

The challenge ahead is credibility at scale. Broadcom's data center moat is structural, not reputational, and no analyst day optimism changes the interconnect fabric already installed inside Google's, Meta's, and Microsoft's infrastructure. MediaTek's realistic path is not displacement but addition: capturing inference-tier programs where cost efficiency matters more than peak training performance, and using the Nvidia relationship to demonstrate manufacturing depth at 3nm. If the company hits its $2 billion 2026 target and converts its second hyperscaler program into a confirmed order, the debate about whether this is a real AI infrastructure company or a smartphone vendor with a good story will resolve itself. Until then, the stock has done the talking.

[BeenRetired] CPU market to grow 5x by 2030, BofA says [graphic] Yahoo Finance CPU market to...

BeenRetired — 6/12/2026 5:41:48 AM

CPU market to grow 5x by 2030, BofA says

Yahoo Finance

CPU market to grow 5x by 2030, BofA says
Story by Daniel Howley
Jun 11 • 2 min read • Updated 13h ago

Key takeaways

Market Expansion: The server CPU market is projected to grow from $35B in 2025 to $170B by 2030, a 5x increase, driven by the global AI data center buildout.
AI Agents Driving Demand: The rise of agentic AI—autonomous digital helpers performing tasks—boosts CPU usage, complementing GPUs in AI workloads.
Key Players & Opportunities: Intel, AMD, Arm-based vendors, along with Nvidia and Qualcomm, are positioned to capture significant market share as CPU demand surges.

The server CPU market is set to grow significantly through 2030 on the back of the global AI data center build-out.

According to BofA Global Research analyst Vivek Arya, the server CPU total addressable market (TAM) will grow to more than $170 billion by 2030 from $35 billion in 2025, a 5x expansion, and well ahead of prior 2030 TAM estimates of $125 billion.

"We view the emergence of agentic AI as a powerful demand accelerant that expands the CPU opportunity and lifts both [Intel and AMD] and [Arm-based] challengers," Arya wrote.

CPUs, or central processing units, have become an increasingly important part of the AI explosion. While graphics processing units (GPUs) continue to dominate data center spending, CPUs from Intel ( INTC), AMD ( AMD), and those built using Arm's ( ARM) chip architecture are set to grab a bigger slice of the AI pie.

The reason comes down to the growth of AI agents, otherwise referred to as agentic AI. AI agents are autonomous and semi-autonomous digital helpers that can perform tasks on a user's behalf.

You can build your own agents using popular tools like OpenAI's ( OPAI.PVT) Codex, Anthropic's ( ANTH.PVT) Claude, and Google's ( GOOG, GOOGL) Gemini. Consumer devices, such as smartphones and laptops, are also beginning to provide agentic capabilities.

While GPUs continue to power AI models, when AI agents take actions based on your prompts, such as scouring your email for a message about an upcoming conference and putting it on your calendar, they're relying on CPUs to perform those tasks.

The continued increase in the use and number of AI agents will only drive CPU demand higher, Arya explained in his note

That, coupled with recent news that Intel is working to build chips for Google and Nvidia, has sent shares of the chip builder soaring 436% over the last 12 months. AMD, meanwhile, has climbed 280% in the same period.

While Intel and AMD stand out among data center CPU vendors, Nvidia ( NVDA) and Qualcomm ( QCOM) stand to grab a piece of the market, as well.

Nvidia already offers its Grace CPU as part of its Grace Blackwell superchip, and it has begun offering its own CPU-based servers. Qualcomm, meanwhile, is expanding into the data center space with its own data center CPU, which it's rumored to debut later this month.

[BeenRetired] "obvious today that we will see growth in next 3 years." Duh.

BeenRetired — 6/11/2026 9:43:26 AM

[BeenRetired] shill ups ASML from $1848 to $2310. Reiterated overweight on WFE biggies. KLA Co...

BeenRetired — 6/11/2026 9:41:44 AM

shill ups ASML from $1848 to $2310. Reiterated overweight on WFE biggies.
KLA Corp., Lam Research, Applied Materials, ASML in focus as Cantor ups price targets

KLA Corp., Lam Research, Applied Materials, ASML in focus as Cantor ups price targets

KLA Corp. ( KLAC), Lam Research ( LRCX), Applied Materials ( AMAT), and ASML ( ASML) were in focus on Wednesday as Cantor Fitzgerald upped its price targets on the aforementioned chip equipment makers, citing continued strong spending.

“We tweak our CY26 [wafer fab equipment] estimate to $145B (or ~32% growth Y/Y) from $140B, with upside likely capped in the $150B territory as a result of lack of clean- room space,” Cantor analyst C.J. Muse wrote in a note to clients. “Moving to 2027, we raise our estimate to $185B from $175B, with industry contacts suggesting high-$180's as max. We reiterate our $200B estimate for CY28 (we are hearing industry can support ~$210B max). It is obviously difficult to have precise granularity that far out today, but considering the extended lead times, shortages of semiconductors, and the time it takes to install clean-room space, it does seem obvious today that we will see growth in the next 3 years. Moreover, if we were to take into account our clear vision for $3T in semiconductor revenues likely by 2029-2030, we continue to see medium-term demand tracking closer to $250-300B. To wit, we initiate a $250B WFE estimate for CY29.”

Muse raised his price targets on KLA Corp. to $2,500 from $2,000, while Lam, Applied Materials and ASML were raised to $425, $650, and €2,000 from $320, $575, and €1,600, respectively. He reiterated his Overweight ratings on the group.

[BeenRetired] TSMC and Nvidia are now putting AI to work inside the chip factory itself TSMC a...

BeenRetired — 6/11/2026 9:17:26 AM

TSMC and Nvidia are now putting AI to work inside the chip factory itself
TSMC and Nvidia are now putting AI to work inside the chip factory itself

Story by Dorian Maddox • 16h

TSMC, the world’s largest contract chipmaker, has begun using NVIDIA’s cuLitho software in live production alongside Synopsys, bringing AI-driven computation directly into the most time-consuming step of advanced semiconductor manufacturing. The deployment ties NVIDIA’s accelerated computing platform to the optical proximity correction and mask-preparation workflows that define how quickly new chip designs reach finished silicon. For an industry racing to build enough capacity for AI accelerators, the move turns the factory floor itself into an AI workload.

Why AI inside the fab changes the production math
Every new process node at TSMC requires exponentially more computational lithography work. Mask layouts for the most advanced chips demand billions of tiny corrections to account for the way light bends through the patterning system. Those corrections, known as optical proximity correction, have traditionally run on massive CPU server farms, and each successive node has pushed those farms closer to practical limits in both time and power consumption.

The decision to move cuLitho into production addresses that bottleneck head-on. Synopsys confirmed that it and TSMC are going into production with NVIDIA cuLitho in a release describing how it is showcasing EDA performance on NVIDIA-accelerated systems, linking the deployment to its Proteus computational lithography software. Proteus is the tool that actually generates the corrected mask data TSMC’s scanners use to print transistor patterns on wafers. By running Proteus on NVIDIA GPUs rather than conventional CPUs, the same correction jobs that once occupied thousands of server hours can finish in a fraction of the time.

The practical consequence for chipmakers and their customers is straightforward: faster mask turnaround means faster design-to-silicon cycles. For companies like Apple, AMD, and NVIDIA itself, all of which depend on TSMC for their most advanced chips, any reduction in mask-prep time translates directly into earlier product availability or more design iterations within the same calendar window. In markets where a few weeks can separate a category leader from a fast follower, compressing the mask schedule can be as valuable as adding an extra design team.

A testable hypothesis follows from this shift. If cuLitho expands beyond mask preparation and into real-time process control, such as etch and deposition feedback loops, TSMC’s cycle time for upcoming nodes like N2 and A16 could fall meaningfully relative to current baselines. That kind of improvement would show up in quarterly capacity and wafer-start disclosures. No public data yet confirms that expansion, but the direction of the technology points toward tighter integration between design software and factory equipment, with AI steering more of the low-level decisions that used to rely on fixed recipes and offline analysis.

Synopsys Proteus and cuLitho in live production
The strongest available evidence for this deployment comes from Synopsys itself. In a company release, Synopsys stated that it, TSMC, and NVIDIA have moved cuLitho into production status, with Synopsys tying the effort specifically to its Proteus computational lithography platform. That distinction matters because Proteus is not a peripheral tool. It sits at the center of the mask-data pipeline, handling the corrections that determine whether a chip design will print correctly on the wafer and whether yield targets can be met at volume.

NVIDIA’s cuLitho replaces the CPU compute layer underneath Proteus with GPU-accelerated processing. The architecture shift lets the same algorithms run on hardware designed for parallel workloads, which is precisely what optical proximity correction demands. Each mask layer involves trillions of edge-placement calculations, and GPUs handle that kind of parallelism far more efficiently than general-purpose processors. Instead of scaling by adding more racks of CPUs, TSMC can scale by loading more jobs onto GPU clusters that are already tuned for similar workloads in AI training and scientific computing.

The three-company arrangement also signals a tighter coupling between the electronic design automation (EDA) industry and the foundry. Synopsys sells the software, NVIDIA supplies the accelerated compute platform, and TSMC operates the fabs where the resulting masks are used. Historically, these roles operated with clear boundaries, with EDA vendors focusing on design tools and foundries treating computation inside the fab as an internal concern. The cuLitho deployment blurs those lines, creating a stack where changes in one layer ripple through the others and where performance gains in GPUs can translate directly into faster time-to-yield for new process nodes.

For competing EDA vendors, the implications are direct. Any design-tool company still running its lithography software exclusively on CPU clusters now faces a performance gap against the Synopsys-NVIDIA combination. That gap will widen as TSMC’s most advanced nodes demand even more computational lithography work per mask layer. Unless rivals adopt similar GPU-accelerated approaches or alternative hardware, they risk longer runtimes, higher energy costs, or both, which can become a competitive disadvantage when foundries and fabless chipmakers negotiate tool choices for their most valuable designs.

Open questions around cuLitho’s reach and measurable impact
Several significant gaps remain in the public record. TSMC has not released its own statement detailing which fabs or process nodes are using cuLitho, nor has it published any wafer-volume or yield data tied to the deployment. Without that information, it is difficult to quantify how much faster mask preparation has become in practice or whether the speed gains have translated into more wafer starts per quarter. Analysts can infer directionally positive effects from the move to GPUs, but hard numbers are still missing.

Independent benchmarks are also absent. Neither Synopsys nor NVIDIA has published detailed runtime comparisons, power-consumption figures, or mask-iteration counts from the production deployment. The Synopsys announcement, accessible through its news distribution system, confirms production status but stops short of offering the kind of technical data that would let outside observers measure the scale of improvement. Without standardized test cases or third-party audits, claims about speedups remain qualitative rather than quantitative.

NVIDIA, for its part, has not provided production metrics beyond what appears in the Synopsys material. The company has discussed cuLitho at industry events and highlighted its potential to cut computational lithography workloads dramatically, but those statements have not yet been backed by process-specific data from TSMC. Public-facing coverage on press channels focuses on the strategic collaboration rather than disclosing node-level performance numbers, leaving investors and customers to extrapolate from high-level descriptions.

Another open question concerns how broadly cuLitho will be deployed across TSMC’s technology portfolio. Advanced nodes such as 3 nm and below stand to benefit the most from GPU-accelerated computational lithography because their masks are the most complex. However, older nodes still account for a significant share of TSMC’s revenue and wafer volume. If cuLitho remains confined to only the very latest processes, its aggregate impact on TSMC’s overall throughput could be modest. Conversely, if the technology scales down to mature nodes where mask sets are reused across many customers, even incremental gains in preparation time could compound into meaningful cost savings.

There is also uncertainty around how quickly other foundries might follow. The Synopsys-NVIDIA-TSMC collaboration sets a precedent, but it does not automatically translate to competitors. Each foundry has its own mask infrastructure, preferred EDA tools, and internal workflows. Adopting cuLitho or an equivalent GPU-based solution would require careful integration and validation. Until more companies publicly commit to similar deployments, it will be difficult to assess whether GPU-accelerated computational lithography becomes an industry standard or remains a differentiating advantage for early adopters.

For now, the clearest takeaway is that AI-style accelerated computing has crossed an important boundary inside semiconductor manufacturing. By embedding GPU-powered software directly into mask preparation at scale, TSMC and its partners are treating computational lithography not as a fixed cost of doing business but as a performance lever they can tune. As more data emerges on runtime reductions, energy use, and cycle-time improvements, the industry will be able to judge whether cuLitho represents a one-time optimization or the beginning of a broader shift toward AI-driven control across the entire fab.

[BeenRetired] Oracle launches AI token bundles as $70B capex plan unveiled [graphic][graphic]...

BeenRetired — 6/11/2026 9:04:53 AM

Oracle launches AI token bundles as $70B capex plan unveiled

+3
•Curated by Copilot•4h ago

Oracle launches AI token bundles as $70B capex plan unveiled

AI bundles debut: Oracle introduced prepaid AI token bundles to 33 early corporate customers, aiming to lock in access to next-gen AI models.

Record backlog surge: Remaining performance obligations jumped 363% to $638B, surpassing cloud backlogs at Microsoft and Alphabet.

Heavy spending ahead: Oracle plans $70B in FY27 capital expenditures, funded partly by $40B in debt and equity, sparking investor caution.

Oracle rolls out prepaid AI token bundles

In its fiscal Q4, Oracle began offering upfront 'token bundles' for AI services, allowing customers to prepay for access to its next-generation reasoning and AI models. CEO Mike Sicilia said the offer is expanding across Oracle’s product fleet, including Fusion applications, and is resonating with customers. Early adopters include Aon Services and Liberty Energy, reflecting corporate appetite for guaranteed AI capacity amid high demand. Seeking Alpha + 1

We’re now expanding that offer across our entire fleet... including our Fusion piece. Early days, but certainly resonating very well with customers.
Mike Sicilia,Oracle CEO

Why Oracle’s backlog now leads big tech

Oracle’s remaining performance obligations soared 363% year over year to $638B, overtaking Alphabet’s $627B and Microsoft’s $460B cloud-related backlogs. Management attributed the surge to massive AI infrastructure contracts, many prepaid or bring-your-own-hardware, which reduce capital needs for data center buildouts. The backlog’s scale offers exceptional revenue visibility and positions Oracle as a formidable AI cloud contender. Stocktwits + 3

Earnings beat overshadowed by $70B spending plan

Oracle reported Q4 revenue of $19.18B, up 21%, and adjusted EPS of $2.11, both above expectations, driven by 93% growth in cloud infrastructure. However, shares fell up to 11% after the company projected $70B in FY27 capital expenditures, plus $20B–$25B in prepayments, funded by $40B in debt and equity. Analysts expressed concern over capital intensity and potential margin pressure, despite management’s confidence in long-term returns. Seeking Alpha + 2

Future scenarios for Oracle’s AI push

If AI demand continues at current pace, Oracle’s prepaid token model and massive backlog could secure multi-year revenue growth and strengthen market share against hyperscalers. Alternatively, slower adoption or competitive pricing pressure could leave Oracle with underutilized capacity and strained margins after heavy capital outlays. The balance between rapid expansion and disciplined investment will likely define its trajectory over the next three years. Seeking Alpha + 2

6 references

1

Seeking Alpha·7h

Oracle begins limited rollout of AI token bundles to corporate clients

2

Seeking Alpha·7h

Oracle expects 34% FY27 revenue growth as it plans $70B net cash capex outlay

[BeenRetired] Musk gets cozy with ASML in MoAPS. ASML Stock Jumps 4% as Elon Musk Says It's E...

BeenRetired — 6/11/2026 8:56:33 AM

Musk gets cozy with ASML in MoAPS.

ASML Stock Jumps 4% as Elon Musk Says It's Europe's Best Company - CoinCentral
Business June 11, 2026 4 mins read
Elon Musk Executes Radical Strategy To Weaponize Chip Manufacturing Ahead Of Historic SpaceX IPO
Business i By Tyler Brooks

The global semiconductor industry is bracing for a total systemic collapse. Elon Musk has arrived to challenge the existing power structures. He is not here to play by the rules of the establishment. The recent appearance by the Tesla and SpaceX CEO at a high-level summit with ASML is not merely a speech. It is a loud declaration of intent that has sent shockwaves through boardrooms from Silicon Valley to the Netherlands.

The world of technology is witnessing an institutional shift that few predicted. Musk is moving to seize control of his supply chain. By aligning with ASML, the undisputed titan of chip manufacturing equipment, he is signaling the end of the current manufacturing status quo. This is not just business. It is a strategic fortification of his empire.

The Architect Of The New Silicon Order
The centerpiece of this disruption is Terafab. This is not a project that operates within the standard industry framework. It is a massive, vertical integration machine designed to bypass the traditional semiconductor foundries that have held power for decades. Musk is positioning himself to dictate terms to the chip industry.

He understands that the future of his companies relies on total autonomy. Whether it is for the brain of the Tesla Optimus humanoid robot or the complex navigation systems required for SpaceX missions, the current supply chain is a bottleneck. Musk intends to cut that bottleneck entirely.

“This is the moment where we decide if we control our own destiny or if we remain at the mercy of global supply chains.”

The urgency in his voice was palpable. He is betting everything on the ability to manufacture the next generation of chips in-house. This strategy of independence is a direct threat to the giants that have historically dictated supply and demand in the silicon space.

Preparing For The Financial Battle Of The Century
The timing of this announcement is calculated. SpaceX is on the precipice of an initial public offering that is poised to be the most significant financial event of the decade. Investors are watching closely. The upcoming IPO represents the ultimate test of the market, and Musk is clearing the path to ensure the company remains untouchable by external interference.

By announcing a formal alignment with ASML before the IPO, Musk is effectively insulating his company from future manufacturing volatility. This is a classic move by a CEO who views his entities as nations rather than mere corporations. He is building a fortress of innovation that the old guard cannot possibly penetrate.

“The era of waiting for third party manufacturers to prioritize our survival is officially over.”

The market is reacting violently to these developments. Competitors are scrambling to decipher the full implications of Terafab. Is it a bluff, or is it the start of a total overhaul of how chips are produced? The consensus among industry analysts is that Musk is rarely bluffing when he puts his reputation on the line in front of the world's most powerful equipment manufacturers.

PS
Me?
It's JUST started.

[BeenRetired] BofA keeps ASML $2,268 PT on $84B '30. BofA Securities reiterated its Buy ratin...

BeenRetired — 6/11/2026 8:30:01 AM

BofA keeps ASML $2,268 PT on $84B '30.

BofA Securities reiterated its Buy rating on ASML Monday and kept its $2,268 price target.

The firm said ASML’s official 2030 guidance targets revenue of €44B–€60B, gross margin of 56%–60%, and operating expenses of €7.7B–€8.5B. BofA thinks ASML can exceed that top end.

BofA’s bull case sees ASML reaching €73 billion in 2030 revenue. In that scenario, higher volumes would absorb more fixed costs — which the firm estimates make up roughly 20% of cost of goods sold.

That would push gross margins above 60%, EBIT margins to 50%, and earnings per share past €90 on or around 2030. ASML’s current gross margin sits at 52.6% over the last twelve months.

ASML Stock Jumps 4% as Elon Musk Says It's Europe's Best Company - CoinCentral

PS
ASML has unmatched tool fleet for Shrink (EUV, ArFi, ArF, KrF), Stack and Package.

[BeenRetired] ORCL traitor dump on +162% CapEx outlay. Q4 FY2026 CapEx: $55.7billion, up 162%...

BeenRetired — 6/11/2026 8:13:02 AM

ORCL traitor dump on +162% CapEx outlay.

Q4 FY2026 CapEx: $55.7billion, up 162% year-over-year CNBC.
Q3 FY2026 CapEx: $39.2billion, already above the $50billion target www.runcheyresearch.com.

PS
Both shill outlets cite CapEx as reason.

PSS
ASML negative?
Hardly.

[BeenRetired] Oracle beats on earnings and revenue, adds $20 billion to planned capital raise ...

BeenRetired — 6/10/2026 7:48:04 PM

Oracle beats on earnings and revenue, adds $20 billion to planned capital raise
Oracle beats on earnings and revenue, adds $20 billion to planned capital raise

Story by Jordan Novel • 3h

Oracle kept its fiscal year revenue guidance intact while raising its profit forecast.
The company beat on earnings and revenue for the fiscal fourth quarter.

Oracle reported better-than-expected earnings and revenue for the fiscal fourth quarter on Wednesday while also raising its profit forecast for the year. The stock dropped 5% in extended trading as the company plans to raise more money to finance its AI buildout.

Here's how the company did in comparison with LSEG consensus:

Earnings per share: $2.11 adjusted vs. $1.96 expected
Revenue: $19.18 billion vs. $19.10 billion expected

Revenue increased 21% year over year in the quarter, which ended on May 31, according to a statement. Net income rose to $4.22 billion, or $1.45 per share, from $3.43 billion, or $1.19 per share, a year ago. Adjusted earnings exclude impact of stock-based compensation.

The company maintained its previous revenue guidance of $90 billion for the 2027 fiscal year, while lifting its forecast of adjusted earnings per share to $8.05. Analysts were projecting $8.01 per share and $88.90 billion in revenue.

Oracle said it foresees raising $40 billion through debt and equity financing, including a $20 billion share sale it announced earlier. That's after raising $43 billion in debt and $5 billion in equity in fiscal 2026, a move that concerned investors due to uncertainty about whether demand for artificial intelligence can justify that much new capital.

For the fiscal year, Oracle reported $23.7 billion in negative free cash flow.

The company called for $1.72 to $1.76 in adjusted earnings per share for the fiscal first quarter, with 27% to 29% revenue growth. Analysts polled by LSEG had been expecting $1.68 in adjusted earnings per share, along with $19.06 billion in revenue, implying about 28% growth.

Revenue from cloud offerings increased 47% in the quarter to $9.91 billion. Analysts polled by StreetAccount had expected $9.97 billion. Software revenue, including licenses and support, totaled $6.82 billion, down 2% but above StreetAccount's $6.93 billion consensus.

Cloud infrastructure revenue jumped 93% to $5.8 billion. The market-leading Amazon Web Services cloud generated $37.59 billion in the March quarter.

Oracle's remaining performance obligation, including revenue that has not been recognized, reached $638 billion on May 31, up 363%. Analysts polled by StreetAccount had projected $595.67 billion. Bank of America analysts, who recommend buying Oracle shares, said over 50% of the remaining performance obligation comes from OpenAI.

[BeenRetired] Samsung tops chip spending as tech firms expand OLED use Samsung tops chip spend...

BeenRetired — 6/10/2026 12:42:02 PM

Samsung tops chip spending as tech firms expand OLED use
Samsung tops chip spending as tech firms expand OLED use

13h· Curated by AI

Samsung’s major spend: In 2025, Samsung allocated 52.2 trillion won to capital expenditures and 37.7 trillion won to R&D, leading all semiconductor companies.

Wider OLED adoption: Sony and OnePlus are testing new OLED TV and phone features, while Hyundai is expanding OLED use in upcoming models.

Cross-industry growth: OLED’s image quality and efficiency are driving uptake in entertainment devices, gaming, and vehicle displays.

OLED self-emissive pixels enable perfect blacks and high contrast

OLED display panels use self-emissive pixels, meaning each pixel generates its own light. This allows the display to completely turn off individual pixels, producing perfect blacks and achieving very high contrast ratios compared to backlit display technologies.

[BeenRetired] No one is investing in chips harder than Samsung right now — and it's not even c...

BeenRetired — 6/10/2026 12:33:37 PM

No one is investing in chips harder than Samsung right now — and it's not even close
No one is investing in chips harder than Samsung right now — and it's not even close

Story by Tyler Lee • 2h

Compared to other semiconductor makers like TSMC, Samsung not only makes chipsets for others, but they also develop their own which is then used in their own products, like smartphones and tablets. So it’s really no surprise to learn that among global chip makers, Samsung was the top chip investor for 2025.

Samsung was top chip investor for 2025
According to a report out of South Korea, it seems that Samsung was the top chip investor for 2025. And making it even more impressive is that none of the other companies came close. Based on the report, Samsung invested 89.9 trillion won in 2025, which is around $59 billion. This includes capital expenditure and research and development.

TSMC came in second place, but like we said, they didn’t come close. The report claims TSMC spent 69.4 trillion won, which after conversion is roughly $45.6 billion. That means Samsung spent almost $13 billion more than TSMC, despite the fact that TSMC is almost the default go-to for many companies like Apple, Qualcomm, MediaTek, and NVIDIA, just to name a few.

The report also revealed that Samsung plowed ahead with its investment. Even though its semiconductor division saw an earnings slowdown in 2023. However, it’s not surprising. Given that there aren’t many companies like TSMC, Samsung, or Intel in the world, any slowdown from Samsung would allow its competitors to pull ahead.

Investment paying offThat being said, Samsung’s investments could be paying off. Samsung beat TSMC to the punch by launching the first 2nm chip in the Exynos 2600. There are also reports suggesting Qualcomm could give Samsung some of its business again for future flagship chipsets. We also heard that Apple could be a potential customer.

But it remains to be seen whether with all these investments, Samsung could potentially overtake TSMC. TSMC has recently admitted that due to demand for AI, they’re struggling to meet that demand. The company also hinted that they could raise its prices in the future. If that happens, Samsung could be a considerably more attractive foundry for some of TSMC’s customers.

The post No one is investing in chips harder than Samsung right now — and it's not even close appeared first on Android Headlines.

[BeenRetired] Samsung tops global chipmakers with nearly 90 tln won in investment Samsung top...

BeenRetired — 6/10/2026 12:29:31 PM

Samsung tops global chipmakers with nearly 90 tln won in investment

Samsung tops global chipmakers with nearly 90 tln won in investment

Story by Kim Han-joo • 15h

SEOUL, June 10 (Yonhap) -- Samsung Electronics Co. spent nearly 90 trillion won (US$59.2 billion) on capital expenditures and research and development (R&D) in 2025, making it the biggest investor among the world's top 10 semiconductor companies, industry data showed Wednesday.

The South Korean tech giant invested 89.9 trillion won, comprised of 52.2 trillion won in capital expenditures and 37.7 trillion won, in R&D last year, according to data compiled by corporate tracker CEO Score.

Samsung's investment far exceeded that of second-ranked Taiwanese semiconductor giant TSMC, which spent 69.4 trillion won.

Despite a sharp decline in earnings in 2023 due to a downturn in the chip industry, Samsung Electronics continued to increase investment.

Its operating profit fell 84.9 percent on-year to 6.57 trillion won in 2023, but the company invested 88.9 trillion won that year, more than 13 times its operating profit.

Industry observers say Samsung's aggressive spending during the semiconductor downturn helped lay the groundwork for the industry upcycle that began gaining momentum last year.

"Given the nature of the semiconductor industry, which requires continuous investment on an enormous scale, recent debates over distributing tens of trillions of won in bonuses and retained earnings during the current boom cycle could place a significant burden on companies," CEO Score said.

[BeenRetired] ASML's surge masks lowball valuation relative to peers Bing Videos [graphic] [g...

BeenRetired — 6/10/2026 12:12:24 PM

ASML's surge masks lowball valuation relative to peers
Bing Videos

[BeenRetired] "74% of wafer revenue from chips 7nm [14%] & smaller" [3 & 5 63%] TSMC reported...

BeenRetired — 6/10/2026 10:59:40 AM

"74% of wafer revenue from chips 7nm [14%] & smaller" [3 & 5 63%]

TSMC reported May 2026 revenue - Search

Copilot:
Short answer: Yes for 7/5/3nm. No for 2nm (not yet broken out). TSMC did disclose detailed revenue shares for 7nm, 5nm, and 3nm in its latest earnings materials, but did NOT provide a numerical revenue percentage for 2nm yet. They only commented on 2nm’s ramp, demand, and timing — not a revenue share. Below is the precise, sourced breakdown.
What TSMC did disclose (latest official numbers)
Q4 2025 wafer revenue by nodeTSMC explicitly reported:

3nm = 28% of wafer revenue
5nm = 35%
7nm = 14%
Advanced nodes (7nm and below) = 77%

These numbers appear consistently across the earnings release, slides, and analyst coverage.

What TSMC did not disclose: 2nm revenue share
TSMC did not provide a 2nm revenue percentage in any official release. Instead, they stated:

2nm entered high-volume manufacturing in Q4 2025
2nm will begin contributing revenue in 2026
2nm demand is extremely strong (Apple, NVIDIA, AMD, Qualcomm already secured capacity)
Analysts expect 2nm revenue to surpass 3nm + 5nm combined by Q3 2026, but this is not an official TSMC figure.

TSMC has not yet broken out 2nm revenue in the way they do for 3nm/5nm/7nm.

Context: Where the “74% of wafer revenue from 7nm and smaller” comes from
That figure comes from Q1 2026 commentary, where TSMC said:

74% of wafer revenue came from 7nm and below

This aligns with the Q4 2025 number (77%), showing sustained advanced-node dominance.

TSMC is historically consistent: They only break out nodes once they are contributing meaningful revenue. 2nm is just entering that phase now.

[BeenRetired] TSMC May revenue jumps 30% as AI chip demand stays strong TSMC May revenue ...

BeenRetired — 6/10/2026 10:21:18 AM

TSMC May revenue jumps 30% as AI chip demand stays strong

TSMC May revenue jumps 30% as AI chip demand stays strong

Jun 10 • 1 min read • Updated 6h ago

Key takeaways

Revenue Growth: TSMC reported May 2026 revenue of NT$416.98B, up 30.1% YoY and 1.5% MoM, with first five months revenue at NT$1.96T, a 30% increase YoY.
AI & HPC Demand: Strong demand for AI-related chips and high-performance computing applications continues to drive growth, benefiting major clients like Apple, Nvidia, and AMD.
Market Reaction: Despite robust sales, TSMC shares fell ~2.2% in Taiwan trading, reflecting market volatility.

TSMC ( TSM) reported May 2026 revenue of NT$416.98B, up 1.5% from April and 30.1% from a year earlier, as demand for advanced chip manufacturing remained robust.
For the first five months of 2026, the contract chipmaker generated NT$1.96T in revenue, a 30.0% increase from the same period last year.
TSMC, which supplies semiconductors to major technology companies including Apple ( AAPL), Nvidia ( NVDA), and AMD ( AMD), continues to benefit from strong demand for AI-related chips and high-performance computing applications, key growth drivers for the company.
Despite the strong sales growth, TSMC shares fell ~2.2% in Taiwan trading on Wednesday.

[BeenRetired] "McDonald’s is not alone — Wendy’s, Taco Bell, and White Castle are also expandi...

BeenRetired — 6/9/2026 4:21:28 PM

"McDonald’s is not alone — Wendy’s, Taco Bell, and White Castle are also expanding AI ordering"

[BeenRetired] "McDonald’s piloting Google-powered AI drive-thru ordering system called ArchIQ"...

BeenRetired — 6/9/2026 4:20:46 PM

"McDonald’s piloting Google-powered AI drive-thru ordering system called ArchIQ"

McDonald’s Testing New AI-Powered Drive-Thru System
McDonald’s is piloting a Google-powered AI drive-thru ordering system called ArchIQ, with an interactive voice assistant nicknamed “Archy”, at five U.S. locations as part of its “McDonald’s Next” strategy Newsweek+1.

How It Works
Archy is designed to automate the entire drive-thru order process — from greeting customers to taking orders, processing changes, and displaying the final order and total on a screen before prompting the driver to “pull ahead” for pickup AOL+1.

Languages: Handles orders in both English and Spanish AOL.
Repeat orders: Can recognize and process “Can I get my usual?” AOL.
Accuracy: Early tests show about 90% of orders completed without human escalation, with over one million transactions processed in pilot stores International Business Times Singapore+1.
Infrastructure: Built on Google Cloud with edge-computing hardware upgrades for faster, localized processing International Business Times Singapore+1.

Goals and BenefitsMcDonald’s CEO Chris Kempczinski says the aim is to deliver both speed and hospitality as more of the customer journey becomes automated KTVU FOX 2+1.

Speed & efficiency: Reduce drive-thru wait times and streamline operations.
Consistency: Minimize human error in high-noise, fast-paced environments.
Staff relief: Free up employees for other tasks, potentially improving in-store service www.breezyscroll.com+1.

Backstory
McDonald’s previously tested an AI drive-thru system in 2024 with IBM, but ended the trial after viral videos showed repeated order errors Newsweek+1. The new Google partnership is intended to address those reliability issues.

Current Status

Pilots: Five test restaurants, including locations in Chicago and New York Newsweek+1.
Rollout: No confirmed plans for a wider rollout yet; McDonald’s is using a “test-and-learn” approach KTVU FOX 2+1.
Future role: Beyond order-taking, Archy may act as a central intelligence platform for managers to monitor operations and identify bottlenecks Moneycontrol.

Industry Context
McDonald’s is not alone — Wendy’s, Taco Bell, and White Castle are also expanding AI ordering Newsweek. The move could mark a major shift in fast-food operations, with AI handling core customer-facing tasks.

Bottom line: If the pilot proves successful, Archy could eventually replace human drive-thru order takers at many McDonald’s locations, setting a precedent for AI adoption in the restaurant industry.

[BeenRetired] Nvidia finally lands Apple as an AI customer. What it means for the stock. N...

BeenRetired — 6/9/2026 11:39:30 AM

Nvidia finally lands Apple as an AI customer. What it means for the stock.
Nvidia finally lands Apple as an AI customer. What it means for the stock.
Story by Adam Clark
Jun 09 • 2 min read • Updated 19m ago

Nvidia stock slipped Tuesday, even though the chip maker has added Apple to its roster of big-name customers. Details, however, are still scarce on exactly how big a deal it could be.

Nvidia shares fell 1.5% to $205.48 in morning trading.

The drop came despite news that Apple will use Nvidia’s graphics-processing units for at least part of its artificial-intelligence revamp, which the iPhone maker announced on Monday.

Apple normally prefers to use its own processors wherever possible and has been a notable holdout against the wave of investment in AI infrastructure that has made Nvidia’s the world’s largest company.

Part of the reason for the minimal share-price move could be that Apple is accessing Nvidia’s hardware via the cloud-computing services of Google rather than buying the chips directly. That might indicate it won’t result in significant new orders, at least for the time being.

“We are collaborating with Google and NVIDIA to run new Apple Intelligence workloads on Google Cloud, extending our industry-leading PCC [private cloud compute] privacy commitments to third-party data centers for the first time,” Apple said in a statement on Monday.

While Apple is working with Google and Nvidia, it also reiterated that much of its AI will operate directly on its devices, which could limit the amount of external infrastructure it needs.

Only Apple’s most advanced AI model—AFM 3 Cloud Pro, which will power AI agents and complex reasoning workloads—will run on Nvidia’s chips in Google’s cloud.

“The lineup reaffirms Apple’s ‘asset-light’ approach to AI versus the in-house builds of frontier labs and hyperscalers,” Oppenheimer analyst Martin Yang wrote in a research note.

Still, the choice of Nvidia hardware to run even some of Apple’s AI services is welcome validation that Nvidia’s chips still play a leading role in the sector, in the face of increasing competition from customized processors and central-processing unit specialists such as Intel and Advanced Micro Devices.

Write to Adam Clark at adam.clark@barrons.com

[BeenRetired] Samsung advanced nodes fully utilized; 2nm customer expand; 1.4nm on track [gra...

BeenRetired — 6/9/2026 11:30:12 AM

Samsung advanced nodes fully utilized; 2nm customer expand; 1.4nm on track

Samsung Electronics Co., Ltd. 2026 Q1 - Results - Earnings Call Presentation (OTCMKTS:SSNLF) 2026-04-29 | Seeking Alpha

[BeenRetired] Samsung HBM4 & SOCAMM2 for Vera Rubin + PCIe 6 SSD ~2X sales [graphic][graphic]

BeenRetired — 6/9/2026 11:23:43 AM

Samsung HBM4 & SOCAMM2 for Vera Rubin + PCIe 6 SSD ~2X sales