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To: neolib who wrote (42935)9/22/2021 5:25:37 PM
From: Joe NYC
of 43951
 
Some people say that if you fiddle with 5950x and release the power cap to a higher power, you can get 30k.

So it will be interesting what power Alder Lake is drawing while doing 30k on Cinebench.

Apparently, Cinebench runs mostly in L2, completely unaffected by the memory system, only partially by speed of L3.

The 8 big cores must be quite good, since they are probably doing 2/3 of the work. So the 8 cores are probably doing 20k Cinebench. Which is quite a bit higher than 5800x which can do about ~15K

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From: neolib9/22/2021 5:28:56 PM
of 43951
 
This is kind of interesting, a EU RISC-V test chip for HPC applications, and done on GF's 22nm FDX process, which I assume was done since that is from Germany.

tomshardware.com

Its a hodgepodge of elements from another of different sources, and pretty low frequency, 1GHz. One wonders what process they will target when they go for actual HPC deployment. I don't think there is any FinFET fab in the EU, so either they turn to TSMC or GF 12nm perhaps, but why limit themselves. They need to target 3nm at TSMC IMHO, assuming a couple of years out...

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To: Joe NYC who wrote (42936)9/22/2021 5:35:05 PM
From: neolib
of 43951
 
But even if the big cores do 2/3rds, the little cores are only taking up 20% of the CPU core die area, so performance/area/w is likely much better. And I'm not so sure the big cores are doing 2/3rds. They certainly are not getting two threads with each thread as good as the single thread Gracemounts clk for clk. So the question is who much different are the clocks? I'd say 60:40 might be closer. In which case 80% of the core die area is doing 60% of the work, and 20% is doing the other 40%.

Remember the hint that Intel might roll out a big.LITTLE device with like 32 little cores? I thought that was an error in the article, but I can see how that might be an OK design.

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To: Joe NYC who wrote (42932)9/22/2021 5:38:28 PM
From: rzborusa
of 43951
 
That was one of the best episodes of Moore's Law. Great view into the industry and the relationship between the key players (TSMC, Apple, Samsung, Intel, Nvidia, AMD).
That page is blank now. I didn't listen to the vid when Pravin posted yesterday.

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To: rzborusa who wrote (42939)9/22/2021 5:54:29 PM
From: Pravin Kamdar
of 43951
 
I still see it here:

youtube.com

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To: neolib who wrote (42938)9/22/2021 6:36:52 PM
From: Joe NYC
of 43951
 
Per area efficiency vs. big core - yea, that must be far more efficient for MT apps. And we also don't know how power efficient each is, as far as how much power per performance. I think Intel is advertising this metric to be also quite favorable to small cores..

Remember the hint that Intel might roll out a big.LITTLE device with like 32 little cores? I thought that was an error in the article, but I can see how that might be an OK design.

Kind of hard to tell how things look outside of Cinebench, in cross section of benchmarks and applications. But if they get the scheduling to work perfectly, it might be a good approach.

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To: rzborusa who wrote (42939)9/22/2021 6:39:48 PM
From: Joe NYC
of 43951
 
It seems Reddit had some technical problems throughout the day. Here is the direct link to the video.


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To: Joe NYC who wrote (42941)9/22/2021 6:51:44 PM
From: neolib
of 43951
 
Us AMD investors need to watch this one carefully. Its one of the few arch features that Intel currently has that AMD doesn't have, and does not appear to have on the near term roadmap. That and the question of whether Intel tries to jump ahead of AMD at TSMC for 3nm.

On wonders if Lisa as V-cache ready to roll in late Oct when Intel is rumored to debut Alder Lake. Would be a nice touch if she rolled it out then, at least if needed.

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To: Pravin Kamdar who wrote (42940)9/22/2021 7:10:21 PM
From: Joe NYC
of 43951
 
One other thing in the video, Daniel mentioned that the lead times are shrinking for AMD and growing for Intel. I am not sure if he was talking about wafers or CPUs, server CPUs in particular. Because there were some anecdotal takes that Milan lead time is up to 20 weeks.

So if this is shrinking, that would be great news.

Overall, since AMD is able to devote more capacity to GPUs, and GPUs are on the lower end of margin dollars per silicon die area, I think the capacity additions from TSMC are continuing even during these tough 2 quarters Q3, Q4)

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From: slacker7119/23/2021 9:45:00 AM
of 43951
 
Digitimes early headlines for tomorrow shows a rumor that AMD and Mediatek are in talks about a JV.


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