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There was some discussion on Twitter, and I also posted a patent that shows a long and narrow silicon bridge connecting / stacked on top of multiple graphics dies, loaded with L3 cache.
Which would bring together both of the AMD architectural home runs - partitioning large chips to chiplets and stacking.
One of the reason why partitioning never quite worked right in the past was because all the units need to work on the same image, and need super fast communication abilities between them. The active silicon bridge accomplishes it.
So the L3 would be stacked and 256 mb and 512 mb were mentioned as possibilities for RDNA3.
We don;t know how much of this will turn into reality. But there is a real chance that AMD will go as far ahead of NVidia with RDNA3 as it did ahead of Intel with Rome / Milan.