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To: neolib who wrote (31159)7/21/2019 5:07:06 PM
From: combjelly
of 32797
 
When and if they do, they will spin off their fabs into a separate company. Which actually might be a good thing for the fabs.

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To: Vattila who wrote (31164)7/21/2019 6:21:02 PM
From: Vattila
of 32797
 
> Robert Haddock

That should be Hallock. Sorry, Robert. :-)

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To: Vattila who wrote (31155)7/21/2019 8:21:10 PM
From: engineer
of 32797
 
wow.....down to single Fin. That is pretty aggressive. The variations on the FET performance was somewhat evened out with the multiple FET that we have on 7 nm to 14 nm. Now going to single FET at 5 nm is going to get really aggressive.

Yeilds at start should be crazy, especially in the circuit performance.

Any info on the voltage scaling on this node? 0.5 V?

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To: engineer who wrote (31168)7/21/2019 9:03:03 PM
From: Vattila
of 32797
 
> The variations on the FET performance was somewhat evened out with the multiple FET that we have on 7 nm to 14 nm. Now going to single FET at 5 nm is going to get really aggressive.

That's an interesting observation. There is also the loss of performance with a single fin, due to lower drive current. Both can be ameliorated by increasing the height of the standard cells and use more fins, while retaining the option to use cells with a single fin in non-timing-critical paths (from the top of my head, I think I read something to that effect, about TSMC's plans for their standard cell libraries). Of course, you lose the density, but you retain some of the power efficiency offered by single fins. But, as you say, you also get increased variance.

> Any info on the voltage scaling on this node? 0.5 V?

This was from a Imec presentation, so I think it is pure research and not directly descriptive of any future foundry process. There were no references to voltage in the SemiWiki article on the presentation.

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From: Vattila7/21/2019 9:32:31 PM
of 32797
 
Eve Considering AMD, Intel for New Eve V2, Aiming for 2020 Launch

"Eve (formerly Eve-Tech), the Helsinki-based startup that crowdfunded and crowd-developed its original Eve V convertible laptop, is officially working on a followup model, CEO Konstantinos Karatsevidis told Tom’s Hardware. It’s currently being referred to as the Eve V2 and the company is planning to launch it between Q2 and Q4 of 2020. […] The original Eve V used Intel’s Y-series CPUs, a decision made in favor of silent operation and battery life over power (although the latter didn’t turn out so well). This time, though, Eve is looking at next-gen AMD laptop CPUs as well as Intel’s U-series offerings."

If they choose AMD Ryzen and the design suggested in the video below, then I might be very interested. That design looks very cool and practical, and if it has a bright screen for outdoor use, I will be sold.

tomshardware.com
theinquirer.net


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To: Vattila who wrote (31169)7/21/2019 10:52:31 PM
From: engineer
of 32797
 
I am not talking about timing critical, I am talking about having enough drive strength to actually drive the output high or low. I am thinking more about yield than circuit performance.

If they took the VDD down to 0.5 or even 0.25 then they might overcome it, but the noise margin of the cell would be horrible. Like .1 volt total noise margin, so the switching zone would be tiny.

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To: engineer who wrote (31171)7/21/2019 11:34:07 PM
From: Vattila
of 32797
 
> I am not talking about timing critical, [...] I am thinking more about yield than circuit performance.

I got that your comment was about variance and yield, but I was just widening the discussion. This is far from my field of expertise, but very interesting stuff nonetheless.

Do you think performance devices can be made with 1 fin cells, or do you think that will be reserved for low power devices? Are Gate-All-Around transistors (nano-sheet/nano-wire), as researched by IBM and announced by Samsung for their 3nm process, the solution to performance perhaps?

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To: Vattila who wrote (31172)7/21/2019 11:44:04 PM
From: engineer
of 32797
 
been 15 years since I was into process science, but I think it all depends on the process used to build the gate all around circuits. Etching a line is much harder than building a layer thickness, so there should be a chance.

BTW - I expect the metal etch widths to stop going down and that metal etch will become the limiting factor in 5nm and 3nm cells. They are already down to almost the theoretical limit of the science.

I miss doing custom cell layout and design. was the funnest part of my career.

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To: engineer who wrote (31173)7/21/2019 11:54:07 PM
From: Vattila
of 32797
 
Thanks.

> I expect the metal etch widths to stop going down and that metal etch will become the limiting factor in 5nm and 3nm cells.

I as I understand that SemiWiki article, that's where Imec's research into Buried Power Rail and Backside Power Distribution can free up some space for metal interconnect, so that as you point out, metal etch width does not have to shrink much further. The commentary I've read about Intel's 10nm process had a lot to do with trying to ameliorate the detrimental effects of shrinking copper wires by switching to cobalt for the finest metal layers.

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To: engineer who wrote (31173)7/21/2019 11:56:20 PM
From: Vattila
of 32797
 
> I miss doing custom cell layout and design. was the funnest part of my career.

Cool! If you don't mind me asking, what kind of designs did you do? Did you work on CPUs?

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