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From: bit36/15/2019 1:06:30 AM
of 33352
 
Semiconductors: Inventory Remains Elevated: Reported Date 6/10/19


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To: FUBHO who wrote (30716)6/15/2019 2:43:11 AM
From: rzborusa
of 33352
 
>, but Intel has a more diverse workforce!

I think the word you're looking for is "perverse". :)

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To: combjelly who wrote (30713)6/15/2019 10:30:10 AM
From: neolib
of 33352
 
They said it was a 12 layer board, and the bump pitch for the interconnects is 130um (0.003" about, for pitch!) So what the line width and space width is would be very fine for pcbs. And what would via hole diameter be, and how are they made. How are the layers aligned and stacked, are they done like laminated pcb, or is the entire structure built up layer by layer by deposition and etch more like an IC?

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To: neolib who wrote (30719)6/15/2019 11:47:56 AM
From: rzborusa
of 33352
 
A few years ago, 10 or 15, a few, I was experimenting with a waste oil burner and purchased a 0.010 carbide drill with a 1/8 shank to fit a die grinder collet. I was amazed that the company listed their smallest bit at 0.001. Even the 0.010 could only do a series of pecks gradually ...

I used a lathe with the die grinder mounted in the tool post and work piece chucked with the spindle locked. It would take quite some time to do one hole through 12 pcb layers otoh there could be quite a gang of bits in sync. Layers could be drilled individually. Copper wire with ball endo... My $0.02

>And what would via hole diameter be, and how are they made

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To: rzborusa who wrote (30720)6/15/2019 12:23:13 PM
From: neolib
of 33352
 
so called high density interconnect pcbs have become very high volume business due to the mobile phones. Those boards are very dense and they use via in pad to make them routable.

I've used these guys for pcb fab a lot, but I've never done hdi designs:

4pcb.com

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To: neolib who wrote (30719)6/15/2019 12:52:18 PM
From: combjelly
of 33352
 
And what would via hole diameter be, and how are they made. How are the layers aligned and stacked, are they done like laminated pcb, or is the entire structure built up layer by layer by deposition and etch more like an IC?

All good questions. None of which I have real answers for. Now I suspect that the vias are probably small enough that they have to be laser drilled. And for small volumes, that can be horrifyingly expensive. That isn't a NRE, though. And I suspect that if it is done more routinely, there is no reason why it can't be cheaper.

Regardless, it would be interesting to know what the costs are. And what effect volume has. If this is something that can be justified in a production run that numbers in the thousands, it can be a real game changer.

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To: combjelly who wrote (30722)6/15/2019 1:05:57 PM
From: neolib
of 33352
 
One wonders why they couldn't let customers do this too, and sell them the component level die, including other vendors doing the same, and then OEM customers can develop their own final package mix of die, for a System on Substrate device.

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To: neolib who wrote (30723)6/15/2019 1:25:59 PM
From: combjelly
of 33352
 
Which is sort of where I am going with this. By making all of their product line as chiplets, and having few I/O ones, AMD can offer a set of packaging services for customers that have enough volume. Outside vendors of other IP like networking, can produce chiplets with Infinity Fabric interconnects or maybe just PCIe X.Y that can be packaged along with AMD chiplets. Eventually others can do the same. Right now there are only two companies that can do this. Hopefully there could be more.

It would be nice to be able to go to a website and being able to select the chiplets and socket type you want. The company then would place and route it for you. A few weeks later you get some boxes with your design. I see no real reason it couldn't be done automatically.

With HBM, the circuit board would be reduced to low speed peripherals, connectors and power management.

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To: combjelly who wrote (30724)6/15/2019 3:54:23 PM
From: rzborusa
of 33352
 
Interestingly for those who don't know the I O chips from AMD start with all available interfaces for memory drives Etc and when some function of the chip is defective it is binned to the functions that are not defective. Making the yeild superb. This blew my mind.

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To: rzborusa who wrote (30725)6/16/2019 3:32:50 PM
From: Pravin Kamdar
of 33352
 
Worth a watch:

youtube.com

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