I thought the previous post was self evident. Please read this whole post before answering as your question may be answered in a later paragraph.
The dies are finished (wafer after production, diced, packaged and tested) and then shipped to an OEM, distributor or direct to a retailer (some retail outlets are large enough to bypass distributors like HP, DELL, IBM or perhaps even Newegg). HP is a special case in that according to other parts of the FY2007 10-K, they account for over 10% of the total computing division sales. Thus they are likely to have return privileges until the retail package is sold to an end user or its used during assembly of a computer (PC, notebook or server).
The point of no return is debatable, but for most it is when the OEM physically places the CPU in the socket. The rest think it occurs on first power on to the PC, notebook or server in question. This is usually no different than a few minutes in most assembly line operations. At that point the CPU is sold. If it fails to work, it is still sold, but cost of sales goes up as a replacement (warranty) is shipped with the return of the defective CPU (arrangements in contracts deal with this kind of thing).
If the OEM is a second, third or lower tier buying from a distributor, the right to return ends at the insertion point (trays) or opening of the retail package (the famed screwdriver shop). Large OEMs, buyers or smaller sub distributors likely would have a return arrangement with the distributor which carries back to AMD. This is the channel that everyone talks of. Generally the smaller you are in total volume (usually by revenue percentage at each stage), the less nice (right of return, etc.) the terms you get.
Typically the right of return ends when the product is sold to a end user (the aforementioned screwdriver shops might buy from a large online retailer like Newegg and get some rights as part of their deal with them). The return percentage of unopened retail packages at that point is very small.
Now in none of this is the value of the unsold inventory ever valued at retail prices, but at the marginal cost to manufacture which is quite small. Some of that inventory of known good dies are held in wafer form and valued at what it cost to obtain and process that wafer. Chartered for example charges about $4-5K for a processed 65nm SOI (CPU grade) wafer. Such a wafer would have hundreds of known good die on it worth $24K or more at sale prices. A 300mm 65nm wafer could have 400+ known good Brisbane K8 DC dies on it. Packaged, they might be worth $30K, but they are still in inventory at $4K at the wafer stage (its less for AMD than Chartered as profits, SGM&A, etc. are not part of cost of production for inventory valuation purposes). Even after packaging and test, those 400+ 65nm DC K8 Athlon64 X2s may be only valued at $8-9K in finished goods inventory. It is cheaper for AMD to keep unordered inventory as wafers or bare diced dies since it takes only 2-4 weeks to package and test them versus from the initial bare wafer stage taking 9-13 weeks (depending on who you ask) to packaged dies. Thus $36 million in inventory could translate into $100-320 million in sold CPUs. And that assumes basic wafer production stayed the same.
The inventory line on the quarterly report is the sum of basic starting materials, WIP and finished goods. Without a breakdown as to what value is assigned to each, changes (delta) between quarters are hard to analyze as to what is happened during the quarter. You can't assume that WIP and material portions stayed the same in each quarter. The real data is in the unpublished inventory journal(s). They could have been (likely were) ramping B3 wafers during Q1, so WIP likely rose in the period in question and a larger cut in finished inventory resulted than your assumption. Also finished inventory fell because they slowed the production of B2 wafers in Q4 and Q1 after the errata was discovered.
Now you might think that idle fab workers are bad and to an extent that is true, but they could be training in immersion for 45nm production and/or running test and prototype batches on that equipment. Not much of that is seen from the outside except for the sample testers and internal engineers. Those fast AKA rocket lots are labor intensive and are folded into the R&D budget. So its likely that they were less idle than at first appearances. Also many vacations likely were scheduled over that time which further reduces their idleness (Germans enjoy many more vacation weeks (6) and holidays (10 federal and 5 provincial) than we do (total of 9 weeks or more)).
Don't make the assumption that Germans work the same amount of hours that a silicon valley engineer does. Although a study done at GE resulted in the finding that American GE engineers spent over half of their working hours in meetings or preparing for a meeting. At GE's German offices, 27% of the time was spent in meetings or in prep, IIRC. The upshot was that even given lower work hours, the longer holidays and vacations, the German engineers resulted in about the same amount of productive work as their American counterparts.
All in all, your original argument that AMD should have known well ahead of time that the quarter was bad, flies in the face of the realities. Latency is key here. It just takes longer for the channel to kick back the results (the more layers it goes through, the longer it takes) and this is well known by most here. Intel has less of a hit because of their much larger corporate sales percentage which are typically ordered well in advance. Also a big seller for AMD is much smaller wrt Intel and subsequently gets less nicer of a deal from Intel than with AMD. Thus a 30% change in the longer latency retail channel hits AMD far harder than Intel at this point. Of course that does work both ways. If the change is up, Intel gets less of a lift than AMD, which usually waits for the earnings report to surprise.
So the fact that AMD waited for all the facts to be in is understandable. They might have hoped that more sell through would happen than what actually did given that B3 was shipping at the end of the quarter. It could be as simple as a big OEM waited an extra week for additional testing before doing a large production run (assemble a bunch of computers with a given configuration). Move 100K of Barcelonas into Q1 and then look at the numbers for an example of much a hit a one week production start delay would do to a quarter (3-7% hit or increase to computing revenues). And AMD would not know that until the OEM informed them of their builds for Q1. And that would be at least a week after it ended. Retail sell through results are at least as slow (both kinds result in money knowingly spent which gets on the back burner at the sender side due to simple human nature (low priority for accounting updates)).
If it was so immediate, why does it take Mercury, Gartner and IDC 5-7 weeks to come out with the sales report for the quarter? By your lights, they should know after a couple of days past quarter end and a couple more days to write the report. The rest of us know the inherent latencies of those processes.