| To: jspeed who wrote (219073) | 12/5/2006 3:59:16 PM | | From: dougSF30 | | | | I would expect AMD to release a die photo to the media, and update their public docs available on their website to contain 65nm die size information, like they did for 90nm parts. I would expect them to provide samples to the usual review sites.
Correct me if I am wrong, but I do not believe their hired folks performed overclocking tests. Certainly they have not made them public, to my knowledge. |
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| To: dougSF30 who wrote (219074) | 12/5/2006 4:05:10 PM | | From: FJB | | | | I would expect them to provide samples to the usual review sites.
Have you lost it? This is the exact same chip they have been shipping for almost two years, except with different power characteristics. |
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| To: kpf who wrote (219055) | 12/5/2006 4:06:26 PM | | From: Elmer Phud | | | | kpf
I don't see why. All else being equal, for a reasonable approximation to yields I'd suggest rather to look at transistorcount than diesize.
Not necessarily so. Die size is a much better predictor within a reasonable range of cache sizes and it includes the size taken by redundancy.
because designs for manufacturability compensate for the above by means of more redundancy for higher transistorcounts.
Edit: Synopsis: For a given design adding redundancy obviously increases diesize and yield. :)
You talk redundancy but you didn't mention cache where it's used. Yes, that will lift yield but at a price. The amount of redundancy you add takes up die size too. There's no reason to add more than you reasonably need, which gets us back to defect density. The lower the DD, the less redundancy you need to add so the lower the die size and the higher the yield. Which makes one wonder if it's related to why AMD reduced the cache size.... |
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| From: FJB | 12/5/2006 4:14:26 PM | | | | | | Qualcomm aims to rival Intel in laptop connectivity
Mike Clendenin
(12/05/2006 7:03 AM EST)
URL: eetimes.com
HONG KONG — Qualcomm Inc laid the ground work for a technology smack down with Intel Corp on Tuesday, saying it would use the recent acquisition of Airgo Networks to invade the connectivity space for laptop PCs and other non-phone portable devices. It also floated another taunt by suggesting its 1GHz Snapdragon platform would be a real nuisance to the PC microprocessor giant.
"Laptop computing is not a niche for us. It is a big and growing area. We not only look at laptops, but sub-notebooks, ultra mobile PCs, Smartphones, wireless PDAs — that whole category of devices where Intel plays today is a great opportunity for us," said Luis Pineda, senior vice president of marketing and product management for Qualcomm CDMA Technologies.
... |
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| To: dougSF30 who wrote (219074) | 12/5/2006 4:14:55 PM | | From: jspeed | | | | The reason AMD did it this way is because it is better from a PR standpoint.
You'll get your anecdotal overclocking stories and opinion pieces like you usually do. But now those benchmarking knuckleheads won't have a clean slate to work with. Instead, the starting point is that a reputable independent analysis says this is an award winning process.
In my opinion, this was a smart move. |
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| To: combjelly who wrote (219011) | 12/5/2006 4:15:59 PM | | From: TGPTNDR | | | | CJ, Re: Assuming the Inq has it right, then at a minimum they are getting more die per wafer than they are getting at 90nm. >
No, that is incorrect, IMO. They are also getting practice at 65Nm. Practice is worth a lot.
IMO INTC Practices a lot more than AMD does on production parts.
-tgp |
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| To: smooth2o who wrote (219058) | 12/5/2006 4:29:46 PM | | From: combjelly | | | | "Boy, talk about the dumbest post of the day... "
Sorry. You are showing a lack of comprehension. Or maybe poor reading skills.
"Maybe you haven't noticed, but all notebooks (and other systems) run power loads at some time (sure you have)."
Yup.
"That requires cooling, so it's not a matter of just sitting there at 14W. "
I suppose you missed the phrase "at idle". Or maybe didn't understand it. Sure, under load it would need cooling. It does have a TDP of 65 watts, after all. Now I will repeat this slowly. Try to pay attention. 14 watts at idle is likely going to require active cooling. That means a fan. Might not if a lot of effort is put into the system design. But likely. At under 4 watts, the AMD 65nm chips won't. Now, especially in an office environment, the chip idles most of the time. Maybe when a spreadsheet is recalculated or a complex web page is loaded is the only time the processor comes off idle for any significant length of time. So we are talking about a fan that has to be on versus a fan that doesn't have to be.
Now do you understand? |
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| To: smooth2o who wrote (219058) | 12/5/2006 4:29:55 PM | | From: justaview | | | | talk about the dumbest post of the day...
You mean there is no market for a low power CPU that does nothing? What about the key chain segment? |
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| To: Elmer Phud who wrote (219076) | 12/5/2006 4:32:10 PM | | From: kpf | | | | elmer
You talk redundancy but you didn't mention cache where it's used.
While I agree cache is where redundancy has most impact on diesize, are you insinuating there is no redundancy in logic in nowadays dfms?
K. |
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