To: Elmer Phud who wrote (219023) | 12/5/2006 2:59:14 PM | From: combjelly | | | "No it doesn't prove anything but it's a pretty good indication nevertheless."
Anything is possible.
"AMD is getting killed on the high end so you'd think they'd do their best to show some top bin parts, if they could."
Under normal circumstances, you have a valid point. But things aren't normal for AMD. For the first time in a long time they are getting commercial SKUs from major vendors. For that market, absolute highest performance isn't a requirement. Focus on moderate power and high volumes is. AMD, with the RS690 chipset has the only integrated graphics solution for Vista with Aero Glass support. Every other solution requires an external GPU.
Which is not to say if they could blow Conroe out of the water, they wouldn't do it. But that has to wait for K8L. Until then, any trade offs for high performance isn't worth it until they are no longer production limited. |
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To: Joe NYC who wrote (218951) | 12/5/2006 3:00:54 PM | From: Rink | | | Joe, re: I wonder why AMD is highlighting the gate length. I remembere that Hans mentioned that Intel did not scale the critical layer on their 65nm as much as expected. Is AMD differentiating themselves here? Or is it unrelated?
I already gave a bit related answer to neolib here: Message 23072894
Intel didn't scale oxide layer at all. It was 1.5nm in their 130nm process, 1.2nm@90nm, and now 1.2nm@65nm.
Can't remember what AMD used at 90nm (slight above 1.2nm iirc; top in the industry seemed to be at 1.2nm-ish; sorry for the vague memory). The mention of 1.05nm for their 65nm process is prove they DID scale it to a reasonable extent. Reason might be leakage related. AMD might have a better combination of technology to combat this problem allowing them to scale oxide (can't be scaled much further though).
Regards,
Rink |
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To: dr_elis who wrote (219030) | 12/5/2006 3:02:16 PM | From: combjelly | | | "On the other hand, to my knowledge AMD does not work with the proven immersion leader ASML,"
If true, that would be new. AMD has been a long time and very loyal ASML customer. At least they were through 130nm. |
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To: dougSF30 who wrote (219034) | 12/5/2006 3:03:04 PM | From: jspeed | | | edit: They are not hiding it. You can purchase a detailed breakdown from Semiconductor Insights (for a handsome fee no doubt).
The fact that these guys gave AMD's 65nm process their award should be enough to tell you that it's good.
edit: semiconductor.com
Semiconductor Insights Logic Detailed Structural Analysis report provides a thorough analysis of the silicon processing steps involved in the construction of this innovative IC. Our report is a comprehensive examination of each level of the fabrication process from passivation to wells.
The Detailed Structural Analysis of the Advanced Micro Devices Opteron Rev G 65nm Microprocessor includes the following information:
Package and Die Overview - Front and back package photos, package x-ray, and a die photo - Package Cross-section
Device Measurements - Die size, die thickness - Number of poly / metal layers - Critical horizontal and vertical dimensions Horizontal: - Minimum metal line width(s), space(s) and pitch(es) - Minimum poly line widths, space - Minimum via and contact sizes and overlap rules - Minimum contact to gate spacing - Minimum NMOS and PMOS gate lengths - SRAM cell area - Standard gate area (a single two-input NAND) Vertical: - Thickness of layers comprising each metal and poly level - Isolation, inter-level and passivation thickness - Isolation edge geometry - Gate dielectric thickness
Cross-Sections and Images - Cross-sections of following critical features: NMOS and PMOS transistors, vias, contacts, metalization, inter-metal dielectrics, and passivation - TEM image of core logic transistor gate and contact structure - HRTEM Lattice fringe image of core logic gate dielectric thickness
Device Topography - SRAM - High magnification SEM images of poly - Core Logic - High magnification SEM images of poly - Bond pad - Die Corner - Power Bus
Substrate Overview - Well and substrate doping profiles from SRP
Passivation and interlevel dielectric profile - Identification of dielectric systems such as FSG, CDO, and barriers
Techniques Applied: - Cross-section - De-layering - SEM - TEM - SRP
Analysis of the above techniques and images will include: - Identification and analysis of key materials - EDS analysis of silicides - Identification and analysis of dielectric layers - dielectric type and deposition method for inter-level dielectrics and passivation - Identification and discussion of unique device features and innovations - Analysis of reliability of process - Identification of process artifacts - Comparison of device to previous process generations as applicable
A comparison of device to competing technologies is also given.
This report comes with 5 hours of analyst time. |
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To: jspeed who wrote (219039) | 12/5/2006 3:09:04 PM | From: dougSF30 | | | The fact that these guys gave AMD's 65nm process their award should be enough to tell you that it's good.
Is that a joke? AMD hires a company, and that company gives them an award, and you want investors to take that company's word for it, or pay them for data that AMD has always released publicly in the past?
Again, what are they hiding? |
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To: smooth2o who wrote (219008) | 12/5/2006 3:09:16 PM | From: rzborusa | | | Smooth, What CJ said and;
The cost to farmers for diesel fuel to grow corn for ethanol makse it totally inefficient However, ethanol fuel is subsidized. Its in style.
Get with it, you'll feel all warm and fuzzy. |
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To: FJB who wrote (219041) | 12/5/2006 3:11:14 PM | From: dougSF30 | | | Dear Robert,
The policy change has not yet taken effect. I'll be more than happy to comply once the voting process is done, and the results are tallied, and any change in rules is made.
Thanks for your understanding! |
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