Advanced Micro Devices - Moderated (AMD)

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Technology Stocks Advanced Micro Devices - Moderated (AMD)

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To: smooth2o who wrote (219008)	12/5/2006 2:46:00 PM
From: combjelly	of 275869

"Over the course of a year (again, assuming 24/7 operation), that adds up to just over $5" But that isn't the only issue at play. At 14W, a Conroe processor is likely going to need active cooling at idle. A 65nm AMD processor won't. In addition, if it is assumed the processor has a low duty cycle when it is off idle, like in an office, the box can be made very compact and would be whisper quiet without using expensive technologies like notebook parts. So the cost to the OEM is lower. And a typical cube farm without hundreds of fans going all at the same time is a lot quieter.

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From: jspeed	12/5/2006 2:46:36 PM
	of 275869

Interesting that Semiconductor Insights was given sample silicon and even included in the 65 nm press release. I wonder if this was done to keep would-be experts from critisizing AMD's new process.

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To: dougSF30 who wrote (219006)	12/5/2006 2:47:33 PM
From: Rink	of 275869

I meant high-k slip for 45nm. This should have been clear from the picture if not from the text (should have left out the '+'). I can't but take your answer as confirmation that you have no hard data to back up your presumption that immersion technology will probably lead to 45nm beyond the timeframe AMD projected. It's only your gut feel. I can live with that. No need to reply. Regards, Rink PS, my 7th post today (incl voting posts). 7's a complete enough number.

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To: Rink who wrote (219009)	12/5/2006 2:48:18 PM
From: combjelly	of 275869

"I can give you a guess (cheaper) but I wouldn't take that as a good answer. " Why not? There is a fair amount of extra steps involved to keep copper from migrating into the oxide layer. Using aluminum would eliminate those steps, plus keep the copper away from oxygen.

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To: Elmer Phud who wrote (219015)	12/5/2006 2:49:34 PM
From: Sarmad Y. Hermiz	of 275869

the article means that if AMD merely gets a slight inclrease in number of good (shrunk) 65 nm die from a 300mm wafer compared to number of good 90 nm (not shrunk) die on same 300 mm wafer, if all these things are true, then it implies yield is lower.

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To: Elmer Phud who wrote (219015)	12/5/2006 2:49:42 PM
From: dougSF30	of 275869

Elmer, what he is saying (but poorly phrased) is: "% good die" yields are lower for AMD's 65nm than for 90nm. However, AMD's 65nm parts are smaller (although at 66 to 70% of the size, not as much smaller than 90nm as they should be), so depending on how much worse the "% good die" yields are, they could still produce more "die per wafer" with 65nm. And that last one is in fact the case, as AMD has told them that is their definition of "launching 65nm with mature yields"

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To: Elmer Phud who wrote (219015)	12/5/2006 2:49:57 PM
From: combjelly	of 275869

"Wrong! With the smaller die size AMD should see better yield in terms of both percent and total die." Personally, I think Fuad or Theo came up with this little gem.

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To: combjelly who wrote (219011)	12/5/2006 2:50:26 PM
From: Elmer Phud	of 275869

CJ We also don't know if the process can or cannot bin high clocking parts. Just because it isn't being done that way doesn't mean it can't. No it doesn't prove anything but it's a pretty good indication nevertheless. AMD is getting killed on the high end so you'd think they'd do their best to show some top bin parts, if they could.

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To: jspeed who wrote (219017)	12/5/2006 2:52:10 PM
From: dougSF30	of 275869

I think that was done because they were feeling bad about their 65nm process, and were worried that when the die size leaked, they would face questions as to whether it really is a 65nm process. :)

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To: Sarmad Y. Hermiz who wrote (219020)	12/5/2006 2:52:19 PM
From: Elmer Phud	of 275869

Sarmad, That's not the way I read it.

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