Advanced Micro Devices - Moderated (AMD)

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Technology Stocks Advanced Micro Devices - Moderated (AMD)

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To: Rink who wrote (218985)	12/5/2006 2:25:56 PM
From: neolib	of 275869

Thanks. BTW, has AMD also retained Al layers all this time. For some reason I thought they had switched to all copper. One would assume the Al layer to be the top, largest pitch layer, for power?

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To: Rink who wrote (219000)	12/5/2006 2:28:48 PM
From: dougSF30	of 275869

Rink, Intel decided a while back not to go that route for 45nm. However, they are producing samples on 45nm now, and plan production shipments in H207, so there has been no "slip" of their 45nm process from that slide, which says 2007.

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To: combjelly who wrote (219004)	12/5/2006 2:31:19 PM
From: dougSF30	of 275869

Well, 90nm had 65W parts up though 2.4GHz, so 65nm is extending this 200MHz, to 2.6GHz.

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To: combjelly who wrote (219004)	12/5/2006 2:32:13 PM
From: smooth2o	of 275869

re: The only circuit enhancement they are claiming is the addition of a Turion low power mode, CIE. That enables the 65nm chips to idle at ~3.5 watts where Conroe idles at about 14 watts. Well, I think according to this, I wouldn't tout it as an advantage :) Over the course of a year (again, assuming 24/7 operation), that adds up to just over $5. Add in power supply inefficiencies, and you might argue $6. Do you think AMD might be splitting hairs at this point? You think "HALF THE POWER OF CORE 2 DUO" is perhaps a little too bold a statement, given the benefits? Are consumers willing to settle for 20-25% lower performance, to save that extra 10W? I suppose if this does become a problem, Intel can turn on more mobile sleep states and get a Core 2 Duo down to 1-2W of idle power. But the sell down this will cause (T-series sales going to less expensive E-series sales in laptops), will probably mean more of a loss for Intel than if Intel simply ceded the "10W makes a huge difference, even at the expense of performance" market to AMD. investorshub.com Thanks to wbmw @IH for looking at this with some reality... Smooth

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To: neolib who wrote (219005)	12/5/2006 2:32:39 PM
From: Rink	of 275869

Neolib, Yes. Silicon layer is followed by copper layers followed by the alu layer. No good idea why the last layer isn't copper as well. I can give you a guess (cheaper) but I wouldn't take that as a good answer. Regards, Rink

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To: Sarmad Y. Hermiz who wrote (219002)	12/5/2006 2:34:27 PM
From: dougSF30	of 275869

Well, yes, that definition of "mature yields" is lame. It would even include the case where you get 1 more 65nm die from a 300mm wafer, on average, which would result in virtually no change in production. I'd still like confirmation from a non-Inq source of the ~125mm^2 die.

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To: Sarmad Y. Hermiz who wrote (219002)	12/5/2006 2:36:14 PM
From: combjelly	of 275869

"The whole point of the shrink is to get more revenue per wafer." Yes. "If yield is poor; and the process cannot produce high bin parts," Don't know if either of these is true. Assuming the Inq has it right, then at a minimum they are getting more die per wafer than they are getting at 90nm. How much, we don't know. We also don't know if the process can or cannot bin high clocking parts. Just because it isn't being done that way doesn't mean it can't. AMD very well could be concentrating on maximum yields instead of high clocks. The manufacturer always has this option, but usually the focus is on performance. Which results in more dumpster filler. In addition, they seem to be focussed on lower power, so that is another trade off against max. clock rate. Another thing we don't know is who the source of this article is. If it is Charlie with the info, then that is a lot more credible than if it is Fuad or Theo.

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To: combjelly who wrote (219011)	12/5/2006 2:38:28 PM
From: dougSF30	of 275869

Why would they focus on lower power at a time when what they really need is more performance? I think the answer is probably: Because that was all they could manage with this process.

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To: dougSF30 who wrote (219012)	12/5/2006 2:42:36 PM
From: smooth2o	of 275869

Maybe not. There's always the "flood the market with low cost parts to gain MS at any cost" theory. This would be my guess as any higher performance parts are post H intro + 6 months. Smooth

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To: dougSF30 who wrote (218971)	12/5/2006 2:43:20 PM
From: TGPTNDR	of 275869

Doug, Re: Any comments would've been about their production stuff (so 65 & 90, not 45), though.> Agreed. Since the comment I think I remember was from last summer and generalized across factories I'd say most likely P4 90. MCW could be a different situation, 65 could be a different situation. I was just pointing out that INTC seems to be going for longer minimum cycle time for 45 Nm while INTC management was talking about relatively long cycle times in their factories. All trade-offs. (I thought you had me on ignore. I tried to PM you a while back and failed on account of Ignore.) -tgp

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