| To: etchmeister who wrote (1911) | 1/7/2011 10:57:04 PM | | From: etchmeister | | | | LOL...all that Ipad hype - TSMC has to increase capex significantly - still believe 22nm Atom could become the T34 of future processors
Ion implant: a new enabler for 32nm and 22nm devices
James Kawski, Mark Merrill, Varian Semiconductor Equipment Associates Inc., Gloucester, MA USA
Over the years, suppliers of ion implant tools have competed mostly on productivity and cost of ownership differentiation. The challenges associated with the migration to 32nm and 22nm have opened up new opportunities and ion implant is one technology that is on track to enable chip manufacturing at future technology nodes.
In the beginning, ion implant was enabling. VLSI circuits could not have been fabricated were it not for the inherent precision of ion implant. Specifically, ion implant enabled accurate threshold adjust voltages on MOSFETs. This enabled low-power CMOS logic and, after a dozen or so technology nodes, our industry has changed the world.
Implant brought three capabilities to the table: uniform dopant distribution across the surface of the wafer, accurate control of the dopant profile and depth, and highly accurate dopant density. These capabilities facilitated dopant profile engineering that was essential for the advent of early CMOS. Without implant, CMOS wouldn’t have seen rapid growth and expansion, or profoundly impacted our lives.1
Historically, implant has had to be highly precise and productive. Unlike deposition, etch, or lithography, implant has never been a consistent or recent enabler of sequential technology nodes. After its initial contribution, it is traditionally extendable over multiple nodes. This created an environment where, for years, implant suppliers competed on productivity and cost. For example, mechanically limited implant throughputs have increased from ˜200 wafers per hour (wph) in 2004 to over 500 wph today. What are the challenges that enable new shrinks, and is implant innovation required?
Technical barriers
The technical barriers for shrinking devices are becoming extremely complicated. The ultra-shallow junctions and short channels in 32nm and 22nm transistor node development are becoming just a few atoms wide. Implant inherently disturbs atoms, resulting in crystal damage that, in turn, creates unacceptable device leakage that will increase a given chip’s power consumption.
We can list a few of these challenges from an implant perspective:
1. Leakage of low power transistors (damage in the crystal lattice);
2. Shallow junction profiles (accurate placement of dopant profile);
3. Shrinking wells and device isolation (accurate placement of dopant due to angle);
4. Process simplification (cost).
Leakage
As devices shrink, effective gate lengths approach the depletion widths of the source and drain junctions. These types of scaling issues induce a variety of short channel effects (SCE) that impact transistor leakage and performance. For the future 32nm and 22nm nodes, implant is uniquely positioned to neutralize these issues through damage engineering applications. Device scaling requires a continuous reduction in junction depths, which are on the order of 10nm at the 32nm node. This scaling is accomplished with an equally continuous reduction in thermal budget.
Click here to enlarge image
The most recent development is the introduction of millisecond annealing techniques such as laser or flash annealing. However, such advanced annealing techniques are not able to completely remove the damage from the implant step, while devices become more sensitive to it. To address this dilemma, a method of precision damage engineering was developed. This enhanced amorphization technique lowers the amorphization threshold of the Si substrate, resulting in a more abrupt implant profile, enhanced amorphization by the implant, and a subsequent lack of residual damage post-anneal (referred to as PTC-II).
Figure 1. End of range (EOR) damage is reduced compared to traditional pre-amorphization implant (PAI) using PTC-II damage engineering process with implant.
Click here to enlarge image
Significant work is underway on in situ implant process modifications that minimize defects and their impact on SCEs and leakage. Through VSEA’s PTC-II process, the amorphous region created by implant is increased resulting in a reduction of self-interstitial atoms that are at the origin of end-of-range defects formed after thermal annealing. Figure 1 illustrates the PTC-II process compared to a conventional pre-amorphization implant (PAI). These end-of-range (EOR) defects are responsible for dopant diffusion and activation anomalies as well as leakage. Reduction and/or annihilation of EOR defects via PTC II reduces junction leakage and minimizes dopant diffusion and dopant deactivation mechanisms enabling better junction formation.2
Shallow junctions
One of the conventional ways to obtain a shallower junction depth is to reduce the implantation energy. However, this approach has reached an impasse where a further energy reduction will lead to a strong degradation in throughput and uniformity. Therefore, new innovative doping techniques have been researched actively in recent years. Among these techniques is molecular doping, or cluster ion implant, which has emerged as a viable approach in the creation of ultra-shallow junctions with high productivity that is free from energy contamination. The Carborane (C2B10H12, CBH) ion is one such molecular specie that has been considered widely in the industry. Because of the size of the ion and the number of dopant atoms included in the molecule, implants made with CBH typically require a 10× lower dose and 13× higher energy.3 CBH is a thermally stable molecule that makes it attractive for ionization in a standard hot cathode ion source, like all other standard dopant ions insuring maximum implanter flexibility and utilization.
Figure 2. Ion-Ioff characteristics of pMOSFET.
Click here to enlarge image
Because of the size of the CBH molecule, shallow junction implants benefit from self-amorphization which creates a lower sheet resistance for the same junction depth. As illustrated in Figure 2, use of CBH in the formation of shallow low resistance S/D extensions has resulted in a 6% improvement of on-current without any deterioration of SCEs, thereby positively impacting device performance.4 CBH appears to be well suited to meet the advanced USJ requirements for 32nm technology and beyond.
Shrinking geometries and isolation
As devices shrink so do the deep wells that isolate devices. In prior node transitions this has not been an issue. However, for 32nm and 22nm nodes there is a problem.5 To eliminate channeling across the wafer, well implants are usually performed with up to 7° of tilt. High energy implants require a thick photo-resist mask, which shadows any implant that is not normal to the wafer.6 Figure 3 shows the shadowing that occurs with a 7° implant. Such an implant may lead to shifts in well boundaries, and poor inter-well isolation.
Figure 3. Illustration of the shadowing that occurs with non-zero degree implants.
Click here to enlarge image
Lateral device dimensions have decreased faster than well junction depths. Photo-resist thickness has therefore not scaled with device size and the problems due to shadowing have increased. To avoid these problems, high energy implants need to be done at a true 0° angle. It has been shown that a true zero implant cannot be done on conventional batch implanters due to a “cone angle effect“6 and that has driven the development of the single wafer high energy ion implanter, which has no cone angle effect.
Cost
One constant in ion implant has been the need to push the present boundaries for production-proven cost performance with higher doses at lower energies. In the past two years there has been growth of a new market for these ultra-high dose (UHD) applications. The most successful of these new applications has been for process simplification at cost-conscious DRAM manufacturers. Traditional CMOS technology required two separate mask steps to dope each of the gates in the CMOS pair with n- and p-type species.
Figure 4. Dual poly gate counter doping process.
Click here to enlarge image
With UHD capability, such as that provided by plasma doping tools, DRAM manufacturers are able to eliminate one poly doping mask step. Instead of doping deposited undoped poly twice, with two masks and two implants, chip fabs can deposit n-type doped poly and with one mask compensate one of the gates in a CMOS pair with p-type dopant inverting n-type poly gate to p-type. This is known as the dual poly gate process (Figure 4).
In addition to very high dose capability at low energy, plasma-based tools provide conformal doping. Beam-line-based tools place all dopant uniformly into the wafer at a variably prescribed angle. Plasma doping tools dope all surfaces and sidewalls isotropically. This opens up enabling applications for CMOS image sensors where conformal doping of shallow trenches has shown appreciable reduction in dark current.8 Future higher-performance low-power 3D transistor schemes may require the conformal doping capability of plasma doping.
Precision materials modification (PMM)
Over the past five years, implant transitioned from dirty, high-risk batch processing to ultra-clean single-wafer technology. This cleanliness opened new growth avenues. Chip makers now have no problem adding implant steps because single wafer implanters have been identified as some of the cleanest tools in the fab. Consequently, investigations into whole new realms of applications have begun to open up. Some of the more promising opportunities include etch stop, photo-resist modification and silicon cleaving. All of these opportunities require high levels of precision in incident beam angle, dose rate, dose uniformity, dopant placement accuracy, temperature control, energy control and defect control. Specifically, PMM applications have huge potential to enable actual scaling through modifications to photo-resist or surface materials requiring patterning.
Conclusion
Implant is returning to the forefront of device design and is now being seen as an enabler for 32nm and 22nm transistors. The challenges of device leakage, shallow junction creation, device shrinkage, and rapidly escalating costs are pushing the limits of Moore’s Law. By providing innovation in a traditionally productivity-driven technology, implant will help move the industry to the next step and encourage device scaling and performance improvement.
References
1. VLSI Research History of CMOS, www.vlsiresearch.com.
2. B. Colombeau, A. J. Smith, N.E.B Cowern, B.J. Pawlak, F. Cristiano, R. Duffy, et al., “Current Understanding and Modeling of B Diffusion and Activation Anomalies in Preamorphized Ultra-Shallow Junctions,“ Mat. Res. Soc. Symp. Proc. Vol. 810, pp C3.6.1-C3.6.12 2004.
3. A. Renau, “A Better Approach to Molecular Implantation,“ Proc. of the 7th Intl. Workshop on Junc. Tech., pp 107-111, 2007.
4. S. Endo, Y. Kawasaki, T. Yamashita, H. Oda, Y. Inoue, “Formation of Low Resistive S/D ?Extension using Carborane Molecular Ion Implantation for Sub-45nm PMOSFET,“ 2008 International Conf. on Solid State Devices and Materials ? Proceedings are to be published.
5. T. Yamashita, M. Kitazanwa, Y. Kawasaki, H. Takashino, T. Kuroi, Y. Inoue, M. Inuishi, “Advanced Retrograde Well Technology for 90nm Node Embedded SRAM by High-Energy Parallel Beam“ Japanese Jour. of Appl. Phys., Part 1 41(4B), pp. 2399-403, 2002.
6. Y. Hai, E.N. Shauly, “Influence of Batch-to-Batch Substrate Variation and Cone Effect on High Energy Implant Distribution Profile,“ 14th International Conf. on Ion Implantation Tech. Proc., pp. 287-290, 2002.
7. W. J. Lee, T. Thanigaivelan, H. Gossmann, R. Low, B. Colombeau, K. Lacey, M. Merrill, A Renau, “Benefits of Zero Degree Single Wafer High Energy Implants for Advanced Semiconductor Device Fabrication,“ 17th Intl. Conf. on Ion Implant Tech , pp. 261-264, 2008.
8. C.R. Moon, J.J. Jung, D.W. Kwon, J.R. Yoo, D.H. Lee, K. Kim, “Application of Plasma-Doping (PLAD) Technique to Reduce Dark Current of CMOS Image Sensors,“ IEEE Elect. Dev. Lett., VOL. 28, NO. 2, pp. 114-116, 2007.
James Kawski received his BSEE from the Rochester Institute of Technology and is manager of market research and communications at Varian Semiconductor Equipment Associates 35 Dory Road, Gloucester, MA 01930 USA; ph.: 978-282-2234; email James.Kawski@vsea.com.
Mark Merrill received his BS in electronic engineering from Maharishi International U. and is general manager at Varian Semiconductor Equipment Associates.
electroiq.com |
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| To: etchmeister who wrote (1913) | 1/27/2011 10:12:17 PM | | From: etchmeister | | | | LOL...all that Ipad hype - TSMC has to increase capex significantly - still believe 22nm Atom could become the T34 of future processors
T 34?!
What long strange trip its been
Timmy Arcuri is now roadkill - scrape him off the pavement |
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| From: etchmeister | 2/10/2011 1:00:32 PM | | | | | | Synopsys and Varian Collaborate on Process Models for Advanced Logic and Memory Technologies
New TCAD Sentaurus Models Address Cryogenic Ion Implantation for Leakage Reduction of Leading-edge Logic and Memory Devices
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Press Release Source: Synopsys, Inc. On Thursday February 10, 2011, 9:00 am EST
MOUNTAIN VIEW, Calif. and GLOUCESTER, Mass., Feb. 10, 2011 /PRNewswire/ -- Synopsys, Inc. (Nasdaq:SNPS - News), a world leader in software and IP for semiconductor design, verification and manufacturing, and Varian Semiconductor Equipment Associates, Inc. (Nasdaq:VSEA - News), the leading producer of ion implantation equipment used in the manufacture of semiconductors, today announced a collaboration to develop Technology CAD (TCAD) models for cryogenic ion implantation. By enabling faster optimization of the cryogenic implant process through simulation, the models derived from this collaboration will speed up process development of advanced CMOS and memory technologies and reduce process development cost and time-to-market.
Ion implantation forms transistor structures in semiconductor silicon through energetic ion beams. These ions disrupt the crystal structure of the silicon, creating end-of-range damage that impacts device performance as devices shrink. To neutralize the damage, Varian's latest generation of high current implanters enables the ion implantation process to occur at reduced wafer temperature (cryogenic implant), resulting in significant reduction of end-of-range damage, minimizing device leakage and widening process margins.
"Today semiconductor manufacturers face tremendous challenges in improving device performance, achieving high product yield, reducing process R&D costs and meeting time-to-market targets. Therefore, it is increasingly critical for simulation to support novel process techniques to reduce technology development time and cost," said Dr Yuri Erokhin, senior director for strategic technologies at Varian. "Cryogenic ion implant has been proven to significantly improve transistor performance and is a key enabler in the manufacture of advanced devices. This collaboration with Synopsys will enable our mutual customers to explore and optimize the cryogenic implant process with simulation, reducing time-to-market."
Through this collaboration, Synopsys will use experimental data from Varian's cryogenic implant process to develop and calibrate models for its TCAD Sentaurus tools, which are widely used by semiconductor companies in the development and optimization of new manufacturing technologies.
"To reduce development time and cost, our customers need TCAD models that are calibrated to the actual equipment used to fabricate the silicon," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "Our joint work with Varian to develop TCAD models for this new cryogenic implant process is an example of our commitment to keep our TCAD Sentaurus tools at the forefront of semiconductor process development."
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS - News) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, California, and has approximately 70 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at synopsys.com.
About Varian Semiconductor
Varian Semiconductor Equipment Associates is the leading supplier of ion implant equipment to semiconductor manufacturers, enabling them to pack more, higher performing transistors into computer chips that are revolutionizing the electronics industry. Varian Semiconductor's products are used by chip manufacturers worldwide to produce high-performance semiconductor devices. Customers have made Varian Semiconductor the market leader in ion implant because of its architecturally superior products that lower their costs and improve their productivity. Varian Semiconductor operates globally and is headquartered in Gloucester, Massachusetts. More information can be found on Varian Semiconductor's web site at www.vsea.com. |
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| To: robert b furman who wrote (1917) | 2/15/2011 12:19:45 AM | | From: etchmeister | | | | Apple reportedly to hand processor orders to TSMC
(my 2 cents - apple could pick up Global Foundries but as far as I understand they are not for sale and apple would run into similar problems with its i phone because QCOM is one of GF's top 28nm customers as far as I understand - it can be tricky not owning a fab - again stick with the ones that actually provide the tools to implement the technology - when two fight each other the third party has a good laugh)
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Nancy Cheng, Taipei; Willie Teng, DIGITIMES [Tuesday 15 February 2011]
Apple is reportedly looking to outsource the production of its A4 processor as well as the next-generation ARM Cortex-A9-based A5 processor to Taiwan Semiconductor Manufacturing Company (TSMC), according to industry sources. The Apple A4 processor is currently exclusively produced by Samsung Electronics, and the previous S5PC100 used in the iPhone 3GS was also developed and manufactured by the Korean company.
TSMC declined to comment on the report.
With Samsung now competing directly with Apple with its own smartphones and tablet PC, Apple is reportedly concerned about leakage of its processor technology to a major rival in the end-use market.
In fact, Apple already began handling some A4 orders to TSMC in 2010 when Samsung's capacity was unable to fulfill strong demand of Apple devices, the sources said, adding that the move at the time was perhaps to test TSMC's capability.
According to Digitimes Research, the iPad 2 will support an enhanced version of the A4 and the A5 will power the iPhone 5. TSMC will initially produce the improved A4, and could likely become the exclusive manufacturer of the A5.
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| To: etchmeister who wrote (1919) | 2/15/2011 1:17:41 AM | | From: etchmeister | | | | again stick with the ones that actually provide the tools to implement the technology - when two fight each other the third party has a good laugh)
I think that's a surprisingly simple concept -
short sellers seem to focus on certain stocks within the semi equip0 group rather target the group itself but than back off.
VSEA was for several days under pressure relative to peers and IMHO they stopped out position with rediculus low volume - and than suddenly the stock moves (up) on high volume.
Tracking LRCX, NVLS and VSEA Varian seems to show the highest volume while moving up.
There are others beside LRCX, NVLS and VSEA but they all have in common that they provide enabling technology to their customers - finally the barrier of entrance appears to "pay off"
Morgan Stanley: Here’s the Best Ways to Play Tablets
By Matt Phillips
Reuters
Morgan Stanley analysts are out with a monster of a note on the dawn of the tablet computer era:
Like smartphones over the past two years, tablet growth is likely to surprise to the upside, in our view, pulling with it market leaders and challenging legacy technology. Importantly, while some tablets will eat into other markets, like PCs, e-readers, and gaming handhelds, more than half of prospective tablet buyers in the US and more than one-third globally view a tablet as an additive device—a bullish signal for the broader technology market. We view Apple and Samsung Electronics as the most likely near-term tablet market leaders in both our base- and bull-case scenarios.
Other stocks closely tied to the tablet revolution? ARM Holdings, Broadcom and SanDisk. Companies that could suffer from the tablet tide include AMD and Dell — due to their exposure to traditional PCs — and companies tied to printers such as Lexmark and Ricoh. |
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| To: Duker who wrote (4) | 2/16/2011 7:40:39 PM | | From: etchmeister | | | | Message #4 from Duker at 3/25/1999 6:00:00 AM
Can Varian make it as a 'one-trick pony' in the ion-implant equipment business?
Semiconductor Business News, © 1999, CMP Media Inc.
March 15, 1999
By Will Wade
Hutcheson says. "Eventually," he adds, "the division looks like an anorexic patient slumped over." The new Varian chip gear maker definitely is a 'one-trick pony,' but for now Aurelio wants to keep it that way. He has no problem in putting all of his eggs into the implant basket, adding that lithography is another market where an equipment maker can successfully be a one-product company. |
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