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Technology Stocks : Intel Corporation (INTC)
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From: TimF8/5/2021 9:50:40 PM
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Intel Rebrands Its Future Process Nodes, Updates Roadmap

Intel has made some major changes and announcements concerning upcoming products and how future improvements to the company’s manufacturing will be communicated. These changes will have a significant impact on how we talk about Intel products going forward.

Decades ago, there was an industry group responsible for defining the characteristics of each new lithography node and an agreed-upon convention for what a new node meant. The actual practice of naming a node in nanometers — 45nm, 32nm, 28nm, and so on — has been divorced from any objective metric for many years now. Today, TSMC, Intel, and Samsung all have different standards for what a given “node” is. TSMC’s 16nm FinFET process retained many of the same dimensions as its 20nm node, but added FinFET. 12nm was then a further refinement of 16nm, but it did not offer the density improvement that the numerical reduction from 20nm to 12nm would imply. These differences between companies are why we have often written that Intel’s 14nm was more comparable to TSMC’s 10nm, and its 10nm more comparable to TSMC’s 7nm.

Intel’s new method for communicating node improvements acknowledges this fact. The company will drop the “nm” from future nodes and refer to them by number alone — Intel 7, Intel 4, and so on down the line. The “A” stands for “angstrom”, the unit of measurement below nanometer. One angstrom = 100 picometers, while one nanometer = 1000 picometers.

Previous nodes will still be referred to by their original nomenclature. Tiger Lake is still considered to be built on Intel’s 10nm process. When Alder Lake launches, however, its “Enhanced SuperFin” won’t be labeled as 10nm++ or +++ or what have you — it’ll be built on Intel 7. Intel 7nm, when it arrives, will be known as Intel 4. It is not clear whether Intel 3 represents a refined 7nm node or 5nm, but refined 7nm seems more likely. Intel’s 7nm is expected to sample in 2022 and ship for volume in 2023, and the “breakthrough” of Intel 20A is expected in H1 2024. This may suggest a two-tier approach where Intel 3 is a refined and polished version of Intel 4, but not a new node. Intel might also introduce 20A for mobile first while holding desktop chips back on the older node, as it’s done since Broadwell debuted in 2014.

Renaming the nodes to a dimensionless number is fine by us. Metrics like “7nm” are essentially dimensionless already. Appending “nm” to the back of the number as if there’s a relationship between the node name and the metric is confusing and encourages people to believe such a relationship exists.

According to Intel, its new node names are based on relative improvements to performance-per-watt, not raw performance. At present, node names are not clearly anchored to any single metric of improvement (performance, power, or area). New nodes have always been occasions for foundries to tout their manufacturing prowess, but the specific improvements of a node transition are particular to itself. The large gap between 28nm and 20nm would seem to imply that the latter would be a major node, but relatively few companies used it. TSMC’s 16nm FinFET (which used the same BEOL as 20nm) was the major node. AMD’s shift from 32nm SOI to 28nm planar silicon at GF did not have a significant net impact on power consumption, even though the node number fell by 4. TSMC’s 5nm offers modest performance and power consumption advances over its 7nm node, but it’s up to 1.8x more dense, compared to power and performance gains in the 1.15x – 1.2x range. I’ve written in the past that new nodes are defined by whatever chum bucket of technology engineers can dump in to make things work better after node shrinks make everything worse, and this will continue to be true.

This slide also reiterates that Intel will introduce EUV at 7nm 4 and extend its usage at 3. At 20A, Intel will introduce ribbonFETs. These are its version of the nanowires and nanosheet technology currently being researched at TSMC and Samsung. Intel 3 will be the company’s last iteration of FinFET, and Intel wants to be in a position of “unquestioned leadership” by 2025. Intel 4 will be a full node die shrink from Intel 7.

PowerVia is Intel’s new technology for power delivery. Instead of running interconnects on top of the transistor stack, all such circuitry will move to the bottom. According to Intel, this allows the top of the chip to be used for signal routing, eliminates voltage droop (with a corresponding improvement in power efficiency), and would allow the company to use either denser signal routing in total or faster wire speeds. Wire speed is a major source of delay in modern chip designs, so improvements here are very useful.

Beyond PowerVias, Intel is working on two new 3D interconnect technologies: Foveros Omni and Foveros Direct. Foveros Omni features copper columns to move power to the top die of the Foveros stack, minimizing the TSV penalty for this kind of bonding. Foveros Omni will also enable Intel to combine different base nodes built on different manufacturing processes together and offers 25-micron solder bumps. Foveros Direct allows for direct copper-copper bonds with 10-micron bumps, boosting overall density. Intel has not revealed if EMIB, its 2.5D bridge interconnect, will continue to evolve.

Intel will introduce 12 layers of EUV at Intel 4 and an unknown for Intel 3 and Intel 20A. Intel has not ordered as many EUV machines as some of its competitors, but it expects to deploy high-NA EUV machines in the future. High-NA EUV is an alternative to multi-patterned EUV, and it’s possible Intel intends to make larger EUV purchases when high-NA machines are finally available.

Intel Doubles Down on Manufacturing ProwessIntel is emphasizing its historic manufacturing chops with these announcements. It’s similar to what the company did back in 2018 for its Tech Day, with the caveat that late 2021/early 2022 will be the first time we see some of the technologies Intel announced then, like Foveros, in shipping hardware.

Intel’s implicit argument to potential foundry customers and end-users alike is that its 10nm troubles represented a deviation from decades of excellent execution, not a new normal for the company. Over the last 30 years, Intel has led the semiconductor industry for much longer than it has lagged it. Appointing a longtime Intel insider like Pat Gelsinger was part of Intel’s strategy to paint itself as returning to its roots.

But Intel isn’t just aiming for a return to its glory days. The company told us that advanced nodes, explicitly including Intel 3 and Intel 20A, will be offered to its foundry customers. The implication is that technologies like Foveros, Foveros Omni, Foveros Direct, and PowerVias will be as well. Intel wants its customers to associate it with manufacturing excellence, whether the silicon inside a given device is x86-based or not. In order to make that happen, it’ll need to offer competitive solutions against rival TSMC.

Last month, I wrote a deep dive into the question of whether comparisons between so-called “CISC” and “RISC” CPUs are an effective way to compare modern microprocessors. Back in the mid-1990s to early 2000s, Intel’s superior manufacturing was key to its long-term success and x86’s eventual takeover of the CPU market. TSMC and Samsung are much more capable than any RISC CPU manufacturer was in that era, while Intel is in a weaker relative position, but the company’s launch roadmap is aggressive.

As scaling becomes more difficult, the absolute contribution of lithography to each node’s performance, power, and area improvements has already begun to drop. Intel’s decision to emphasize alternative interconnect technologies alongside an eventual shift to ribbonFETs acknowledges this trend. We don’t know how Foveros, Foveros Omni, or Foveros Direct will compare with offerings from TSMC, but any advantages Intel can wring from its new interconnect methods can be used to lower overall x86 power consumption, improve performance, or both.

Oh, one last tidbit: Intel’s Meteor Lake taped in this quarter. Tape-in means the various design groups contributing IP blocks to Meteor Lake have submitted their work to the final product database. This is distinct from tape-out, which refers to sending a completed design to the factory for manufacturing. Meteor Lake is expected to launch in 2023, so we’re still a few years from commercial volume.

extremetech.com
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