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AMD 29.54-7.4%Aug 23 4:00 PM EDT

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To: engineer who wrote (31173)7/21/2019 11:54:07 PM
From: VattilaRead Replies (1) of 32244
 
Thanks.

> I expect the metal etch widths to stop going down and that metal etch will become the limiting factor in 5nm and 3nm cells.

I as I understand that SemiWiki article, that's where Imec's research into Buried Power Rail and Backside Power Distribution can free up some space for metal interconnect, so that as you point out, metal etch width does not have to shrink much further. The commentary I've read about Intel's 10nm process had a lot to do with trying to ameliorate the detrimental effects of shrinking copper wires by switching to cobalt for the finest metal layers.
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