SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : AMD, ARMH, INTC, NVDA
AMD 81.81-1.0%Aug 13 3:59 PM EDT

 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext  
To: TGPTNDR who wrote (30705)6/14/2019 3:10:43 PM
From: neolib of 37793
 
One of the articles I linked recently, directly commented on that issue, but it was wrt to the chiplet die attached to the substrate, in order to get all the chiplet surfaces at the same height for the heatspreader. The way they did it was via careful control of the copper posts they are using for the interconnects. They claimed it gave better stack control than plain solder bumps.

I think by far the big reason for chiplets is yield. It allows a 64 core chip to be implemented on 7nm but with only 70mm2 die or so. That can yield, whereas Intel's 500mm2 monsters can't.

As to whether there is any thermal advantage, that I'm less sure of, because a little thickness in the heatsink at the contact can spread that laterally too. As far as the die is concerned, the heat per unit area is approximately independent of adjacent heat sources, its assumed the heat all goes normal to the surface and into the heatsink. Its just the delta between the silicon and the heatsink that counts.
Report TOU ViolationShare This Post
 Public ReplyPrvt ReplyMark as Last ReadFilePrevious 10Next 10PreviousNext