|EUV as Pizza|
Perfecting the Recipe
by Bryon Moyer March 27, 2017
What’s the most important thing for the perfect pizza? This isn’t a fair question, of course, because there’s no definition of “perfect” when it comes to pizza. OK, maybe there is, but each person has their own. But stay with me for a sec here: for a certain style of pizza, you need an oven that’s over 500 °F – higher than home ovens can go, for sure. And the right old-school wood-fired ovens can do that.
So if you’re in search of that perfect pizza, the first thing you might have to do is to splurge to get an oven that will finally give you the heat you need. You might play with the amount of wood you use, the best pizza positioning to ensure even heating, and the best oven placement for not burning the house down before you’re satisfied that you’ve nailed it. It could take a lot of work – probably more than you expected.
And then, at last, you declare the oven problem solved. Do you now have the perfect pizza? Well… not yet. Now you need to make sure the dough is perfect, and there’s the sauce, and then there’s how you assemble it – how thin you make the crust, how much sauce, which and how many toppings. You’ve still got some work cut out for yourself.
That feels like where we are with EUV. We now have our oven – the EUV source. Still needs some tuning, but, as of last year, it feels like the worst is behind us. IBM, GlobalFoundries, and Samsung presented at IEDM last December, introducing a 7-nm FinFET process platform that, for the first time, included EUV. So the technology is finally starting to migrate towards production, and not just at Intel. But there’s the matter of this laundry list of things that need to be tidied up before we can launch. We got a rundown of the issues at the recent SPIE Advanced Litho conference, so let’s review them.
While you may think that we’ve been over this hump for a year or so, the source still tends to grab ongoing attention. ASML is still the leading voice here, although there was a mention of Gigaphoton as a credible second source. Intel has 14 scanners; ASML says there are 18 units on back order – no small thing with a price that they say is on the order of hundreds of millions of dollars per unit. They’re looking at a production ramp in 2018.
The NXE3300B is the incumbent model at the moment, but the next version – worthy of a number change – will be the NXE3400. It’s expected to support 5-nm processes and DRAM below 15 nm with 125 wafers/hour-throughput. The numerical aperture (NA) will remain at the current 0.33, giving 13-nm resolution. Critical dimension uniformity (CDU) will be 0.3 nm; the depth of field will be 100 nm; and they’re expecting 20% exposure latitude.
Power is now over 200 W – 205 to be precise. But the target for high-volume production is now 250 W, so there’s still work ahead.
A high-level parameter to watch is availability, which has risen to over 80% – but needs to be over 90% for economic high-volume production. There are a number of items that can take the machine down – they’re undergoing extreme tune-ups.
Droplet generator: I don’t recall this being on the hit parade in the past, but apparently the lifetime of the droplet generator hasn’t been what was hoped, running at present at around 80% of expectations. You may recall that this whole system works by carefully timing drops of molten tin and then zapping them – not once, but twice – with a laser as the droplet falls. So this is the critical element that feeds the beast.
While more is needed, they’ve improved that lifetime by 3.5 times as compared to last year (Samsung claims a 5X gain), and improvements in the works are expected to further triple the lifetime. That aside, Samsung is also hoping for faster tin refill to maintain uptime.
The collector: You may recall this from past years – it’s the metal shroud that takes the EUV from the zapped droplet, which emanates in all directions, and focuses it into the beam that will make its way to the wafer. And it is also degrading too quickly. So ASML has a newer version coming that should address this maintenance issue.
Pellicles: We talked about these in more detail last year; they’re the mask “cover,” if you will, that keeps fall-on defects out of the focus region so that they won’t print. Fundamentally, they have a working solution now, although, again, it can be improved. First, there’s no change to the fact that they’re still needed. Intel said that they’re seeing fall-on defects at higher levels than ASML is claiming. Defects on the pellicles themselves remain, although the numbers have been reduced. This really needs to get to 0 to be acceptable.
The pellicle material itself is OK, but Intel could do with better transmissivity and the ability to handle higher power when that becomes available.
Mask inspection and defectivity: The quality of blank masks has improved to the point where they can map the defects and then shift the pattern slightly to keep those defects out of critical points. There is still, however, no actinic (i.e., illuminated with the same light frequency as is used for exposure) inspection available for patterned masks.
Edge-placement error: I must not have been paying attention, since this was a new term to me this year. And yet it’s a hot issue (meriting its own TLA: EPE) – not just for EUV, but also for 193i and, in particular, for multi-patterning. It’s described by KLA-Tencor as a convolution of overlay and CDU – anything that can make edges on multiple layers fail to line up. That would also include etch steps as well.
Applied Materials has focused in particular on improvements to etch, but the ultimate solution requires yet more development so that self-aligning techniques with new materials and highly selective etching can use hard masks, rather than litho, to define edges, granting litho a bit of slop.
One approach being discussed to eliminate machine-to-machine variation is to dedicate machines to a particular lot. If lot A uses scanner X for a critical layer, then all subsequent exposures should use the same scanner – at least for other steps involving edge placement. Obviously this reduces manufacturing flexibility, so it’s likely to be used reluctantly.
Line-edge roughness (LER): This, along with the related – but different – line-width roughness, is a perennial issue. And I learned more about the diabolical triangle connecting EUV dose, resolution, and LER. Its origins lie in – surprise! – the source power we’ve been agonizing over for the last many years. Turns out that, even with the improvements in EUV power, ordinary deep-UV lithography delivers 14 times more photons to the resist on the wafer than EUV does.
The thing about photons is that they arrive and position themselves somewhat randomly. If you have enough of them, they average out and, ultimately, fill the expected areas of the resist with smooth edges. But with EUV, we can’t wait long enough for this averaging to be effective – we’d never make any money. So you end up with these ratty edges that scatter the poor electrons as they try to make their way through.
High-NA: The standard NA is 0.33; ASML is working on a lens that will raise the NA to 0.5 or higher. Interestingly, this will be an “anamorphic” lens – the x-direction scale will be different from the y direction (so, for example, a circle would end up looking like an ellipse). The new lens has a smaller field, which means less exposed in one shot, which means more shots per wafer – which means slower. They’re compensating for this with faster wafer and mask stages.
Interestingly, the ASML paper describing this includes a roadmap – with no years labeled for availability of this solution. So this may be a ways out there yet…
Mix-n-match: Of course, not every layer on a chip is going to require EUV – which is good, since there’s not enough of it to go around (and what there is is expensive). That means, for instance, SAQP for metal lines and then EUV for the block mask. (I was confused as to what a “block” mask is; it’s effectively the same as a “cut” mask. With aluminum, you can create lines and then cut them after. But with copper and dual-damascene, you interrupt the trenches with a block that defines the end of the lines and then fill with metal.)
This means that wafers will be going back and forth between conventional and EUV machines – creating a need to match characteristics to reduce yet another source of variation.
So that’s a super-fast rundown of EUV goings-on. I downloaded the EUV related papers, and there were – count them – 59 papers. Which is why I’m not even attempting detail. There’s lots more to explore in those papers.
SPIE proceedings (membership or attendance required – you may need a friend)