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To: THE WATSONYOUTH who wrote (127139)2/11/2001 9:54:47 PM
From: Scumbria   of 186740
 
Watson,

It was at MPF in October. Unfortunately I chucked all my MPF stuff last week, in a desperate effort to clear out my home office.

Scumbria

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To: Scumbria who wrote (127142)2/11/2001 10:08:56 PM
From: THE WATSONYOUTH   of 186740
 
It was at MPF in October.

Don't you guys read this stuff?? This VERY interesting link has been on this thread multiple times. It's two cores/chip.... 4 chips/module....etc. Get it???


chips.ibm.com 

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To: Scumbria who wrote (127141)2/11/2001 11:01:25 PM
From: fyodor_   of 186740
 
Scumbria: I think those are different terms for the same technique.

Well... it isn't, it seems... ;)

If you check out the article from The Microprocessor Report that TWY linked:

chips.ibm.com 

It shows 4 dies in an MCM with each die containing 2 cores and one L2 cache.

-fyo

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To: Tony Viola who wrote (127116)2/11/2001 11:46:07 PM
From: Rob Young   of 186740
 
<IA64: we got a look at McKinley booting Linux, just one week after first silicon.>

Wow... if it stays on schedule like Itanium, maybe it
shows up in March 2003.

"After several slips, Itanium achieved first silicon in August 1999; prototypes are functioning well and are currently available."

Rob

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To: Rob Young who wrote (127145)2/12/2001 12:10:31 AM
From: Tony Viola   of 186740
 
Rob, I think it's pretty common knowledge that Merced wasn't designed for the clock speed that is needed today, hence a few steppings have been needed to get it up to snuff. Takes time. McKinley, OTOH, is a newer design and clock speed requirements were taken into account more from the start. It shouldn't need those kind of steppings.

So what platforms are you attached to that won't be cannibalized by McKinley based servers?

TV

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To: chic_hearne who wrote (105101)2/12/2001 12:16:11 AM
From: mishedlo   of 186740
 
Damn, am I supposed to bail on my IBM puts purchased recently at 114 and thank my lucky stars I am ahead?

Keep that talk up and you will cause some clown $ to be thrown that way.

M

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To: Jim McMannis who wrote (127137)2/12/2001 12:26:52 AM
From: Paul Engel   of 186740
 
Jimbo - re: "Like I said, I think there could be a place for Timna2 in portable devices but wonder if it's worth all the development costs. Maybe Intel just didn't want to put all those Engineers out on the streets."

Sure.

Otherwise AMD might hire them to figure out how to make a notebook CPU - or an SMP chip set.

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To: Tony Viola who wrote (105105)2/12/2001 12:28:29 AM
From: mishedlo   of 186740
 
Actually they are not dead at all. Charles Schaub converted all its trading from IBM to client/server and back again when, to put it mildly, the results were quite undesirable.

Storage, as well as MIPS (million Instructions Per Second), etc are total overated on other platforms. Storage cheaper you say (yeah, right). IBM can achieve 95% utilization on its storage devices, while C/S systems lock up at half that. Ellison admitted that himself. No joke. So... storage is cheaper (byte for byte) BUT you need 2-3 times as much to break even.

Same with processor power. IBM makes very effective use of processor cycles. Other platforms running Oracle .... Uh sorry no way.

Damn. Maybe I should join Chic and hop on the IBM crusade.

PS, I worked in the industry for 20 years, I am confident I know what I am talking about. Wish I could find the quote from Oracle CEO to prove it.

Mainframes dead. No way.
IBM a good buy (I doubt it strongly).

M

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To: Scumbria who wrote (127138)2/12/2001 12:29:27 AM
From: Paul Engel   of 186740
 
VOLUME 13, NUMBER 13
OCTOBER 6,1999
REPORT

Power4 Focuses on Memory Bandwidth
IBM Confronts IA-64, Says ISA Not Important
by Keith Diefendorff
Not content to wrap sheet metal around
Intel microprocessors for its future server
business, IBM is developing a processor it
hopes will fend off the IA-64 juggernaut. Speaking at this
week’s Microprocessor Forum, chief architect Jim Kahle de-scribed
IBM’s monster 170-million-transistor Power4 chip,
which boasts two 64-bit 1-GHz five-issue superscalar cores, a
triple-level cache hierarchy, a 10-GByte/s main-memory
interface, and a 45-GByte/s multiprocessor interface, as
Figure 1 shows. Kahle said that IBM will see first silicon on
Power4 in 1Q00, and systems will begin shipping in 2H01.
company has decided to make a last-gasp effort to retain
control of its high-end server silicon by throwing its consid-erable
financial and technical weight behind Power4.
After investing this much effort in Power4, if IBM fails
to deliver a server processor with compelling advantages
over the best IA-64 processors, it will be left with little alter-native
but to capitulate. If Power4 fails, it will also be a clear
indication to Sun, Compaq, and others that are bucking
IA-64, that the days of proprietary CPUs are numbered. But
IBM intends to resist mightily, and, based on what the com-pany
has disclosed about Power4 so far, it may just succeed.

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To: Paul Engel who wrote (127150)2/12/2001 12:35:36 AM
From: Scumbria   of 186740
 
Paul,

We were all wrong. Per Watson's post, Power4 ships with 8 cores to a package.

Scumbria

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