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To: Joe NYC who wrote (216838)11/16/2006 5:59:19 AM
From: pgerassi
of 273510
 
Dear Joe:

I never sait it did. But the core has them. 3 of them in Rev F and G cores, and 4 in Rev H. AMD just chose not to route them to pins (apparently).

Check pin counts. With 940 pins in AM2, where could they have gotten the 106 pins needed for another 16/16 HT interface? And still allowing for seperate power supplies for each core, the XBAR and HT link, and the MCT/DCTs two seperate DDR2 channels. 106 pins are a lot to free up although some could be shared with the other HT link. S1 does have only 638 pins, but it may have only 1 DDR2 channel with lower amounts of power/ground pins due to the 35W TDPmax wrt 120W TDPmax of the desktop AM2. Judging by current requirements, AM2 has to have 3.4 times the total number of power and ground pins of S1. Those two changes could easily save 302 pins. And then there is those pins that will be needed for DDR3 and many other things coming up in the near future. Adding the 267 pins to AM2 to socket F could allow for 2 or 3 additional 16/16 HT links with some sharing.

they could have increased it, but there certainly were enough pins in Socket 939, which AMD just didn't connect.

Again, they needed a bunch for the second completely seperate DDR2 channel. If you look at the old 940 and 939 pin layouts, you can see the large amount of pins taken up by duplicating the control, clock and addressing pins to allow for unbuffered memory in the 939 over that of the 940. The you need to add pins for the higher TDPs of the FXs. And keep a few more spares JIC. After all that, more than 106 pins were used negating one whole 16/16 HT link and part of another. Socket AM2 just uses the same basic layout of 939 but uses a few more of the spares from the second negated HT link for seperate the power planes for up to 4 cores, the section holding the XBAR and HT link and the memory controller section. And a few more for DDR2 to allow the channels to be totally independent.

And there is a cost for more pins in additional layers for the MB, more routing, package size and package cost. That is not trivial for the tens of millions made each quarter. Server and enthusiasts are willing to pay the extra price needed for the extra functionality. If you want all of that, you will have to pay for socket F MBs and all of the associated costs. And because they only connect one HT link, they have three or four chances to find a good one. With all of HT links socket F allows, AMD has to verify that all are good just like they did for socket 940. MB makers could use the other two HT links in 2## Opterons, but few used more than one on one socket.

And if you wait for a few quarters, vendors could make dual and multi AM2+ socket MBs. By that time AMD will still have only three current sockets used by their latest stuff, mobile S#, desktop AM# and server F#. There are two sets of things here and AMD has control of only one until recently. The first set is what is possible in the current designs. The second is what vendors design their boards to actually use of the possibilities. MB makers could have put 6 DIMM slots in 939 MBs, but chose to only put four. They could have put 8 per 940 sockets, but few did like HP's 585. Some could have used 4 HT links for I/O in 2S MBs, but none did. They could have connected the NB and SB chain back to other 2S MB socket for additional reliability, but none did. AMD has to check for everything that is available to be able to be used, but MB and OEM designers may not make use of them.

I am hoping that that AMD has learned from the Socket AM2 f-up (that it had to go to Opteron socket for 4x4) and will not repeat the same mistake with AM3. But my money is on AMD making the same mistake again. Something like 4x4, or Torrenza capability should be available to all AM3 processors.

First AMD didn't F'up with AM2. Intel did another kludge job. And you want the functionality for free instead of having to pay for it. Some of the goes to AMD, but the rest has to go to the various vendors that make use of that as an incentive to provide it. Just like you have to pay more for SLI or Crossfire enabled MB over one that can't. If you can wait for it, many of those things will be available gratis as the luxury becomes basic required functionality by the market. Like the mobile Semprons gaining 64 bit functionality with the AM2 and S1 versions.

As for Samsung going 1Gb and up, good for them. We have been stuck with 512Mb for far too long. There was no good reason for needing DS DIMMs to get 1GB for the last 3 process generations (180nm, 130nm and 90nm, going now to 65nm).

Pete

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From: BUGGI-WO11/16/2006 6:31:06 AM
of 273510
 
New HP (AMD) Server

I wasn't aware, that HP introduced new AMD Servers - you?
Both are Quad-Core ready. ;)

web.amd.com

DL365
web.amd.com

DL685 (Blade)
web.amd.com

BUGGI

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To: DRBES who wrote (216846)11/16/2006 6:42:10 AM
From: j3pflynn
of 273510
 
DRBES - I wonder if this means they'll make some sort of NB analog with additional functionality, or if they'll still have to go through the NB to get to the Intel processor?

Separately, Intel announced it has licensed its front-side bus (FSB) to both Altera Corp. and Xilinx Inc., so they can build FPGAs that link directly to Intel CPUs for a variety of high-performance computing applications. AMD earlier this year announced it was working with Altera and a handful of smaller companies on a similar plan with cHT.

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To: eracer who wrote (216843)11/16/2006 6:48:56 AM
From: pgerassi
of 273510
 
Eracer:

AM3 isn't relevant. It isn't expected to launch until mid-2008 when AMD supposedly begins their 45-nm transition. Desktop Kuma launches in H2 2007.

HT 3.0 will be available in socket AM2+ and F+ in 2007, not 2008. Perhaps some functionality may be missing, but to get 4GHz HT (2GHz clock) in Kuma requires HT 3.0 as HT 2.0 only clocks to 1.4GHz. You would see that if you would have checked hypertransport.org .

I was just keeping my reply on-topic (desktop Kuma) rather interrupting with an AMD HT3.0 server infomercial.

Still trying to reduce Kuma by miscomparing it to AM2 FXs rather than mainstream AM2 X2s. Although desktop Kumas can be put into socket F packages to replace 90nm FX-70s and FX-72s and still be considered desktop. So multisocket Kumas would be back in the discussion.

So does AMD, apparently. AMD roadmaps show future 4x4 platforms are on Socket-F+ instead of AM2+.

That doesn't prevent any of the MB vendors from making them. I'm sure if a large customer like Dell or HP asked, AMD would allow it. They made A64 X2 3600+s and Turion MK-36s by request. Tyan has a dual socket AM2+ MB available.

We know the performance increase from 1MB total L2 to 2MB total L2 was rather small, so small that AMD killed the AM2 version quickly after launch (but did introduce the 5200+ later). No sense believing that moving from 2MB L2 to 3MB total L2+L3 is going to make a huge performance increase.

Depends on where the L3 is attached. If it is by the MCT, even IGPs will see a large latency reduction. As for 939 to AM2, the cache size was the same and fully independent. So the only thing changed was DDR1 to DDR2. Some games did see a bigger change than 5% between 640KB to 1152KB effective cache. Most of those likely had a working set larger than 640KB. Given that most of the benchmarks used by these reviewers have working sets smaller than L1, of course they don't see much benefit with larger L2s.

Going from 640KB in mainstream AM2 to 2688KB in mainstream AM2+ will likely have more than twice the impact of going from 640KB to 1152KB, especially since most user applications are single threaded. To get a better handle on what improvement will be seen, more needs to be revealed about how the L3 is organized (ways, hit latency and banks) and attached (buses and where).

There you go off to lala land again talking about late-2008/early-2009 CPUs instead of Kuma.

No I didn't. AMD has IGPs from its ATI division right now and nVidia has IGPs for AMD as well. IGPs for AMD CPUs have been around for years and continue to be available. They are part of many chipsets. Since they are used for AM2 based CPUs, they should still be around for Kuma. Even Intel has them, poorly performing ones, of course.

Why do you have Fusion on the brain?

Pete

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From: BUGGI-WO11/16/2006 6:58:03 AM
of 273510
 
New SUN Workstation next week(s)?

developer.novell.com

BUGGI

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To: KeithDust2000 who wrote (216859)11/16/2006 6:58:28 AM
From: j3pflynn
of 273510
 
Keith - Bit thin evidence, but you never know...

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To: fastpathguru who wrote (216868)11/16/2006 7:01:13 AM
From: j3pflynn
of 273510
 
fpg - Interesting, I'd missed that as well.

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To: Rink who wrote (216871)11/16/2006 7:06:09 AM
From: j3pflynn
of 273510
 
Rink - Agreed. I think Theo is talking out his *** on this one.

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To: DRBES who wrote (216846)11/16/2006 7:31:08 AM
From: cruzbay
of 273510
 
"The resulting improvements fall short of creating a cache-coherent version of Express; as such, they do not provide all the underpinnings offered by the coherent HyperTransport (cHT) technology at the heart of AMD's Torrenza program. Nevertheless, functionally, the Express extensions aim to address many of the same core uses as Torrenza, including providing a standard connection between a processor and accelerators for functions that could include networking and XML processing.

In that sense, a big part of the motivation for Geneseo is stealing the wind from AMD's sails as the latter tries to capture interest from third-party chipmakers and OEMs.

Separately, Intel announced it has licensed its front-side bus (FSB) to both Altera Corp. and Xilinx Inc., so they can build FPGAs that link directly to Intel CPUs for a variety of high-performance computing applications. AMD earlier this year announced it was working with Altera and a handful of smaller companies on a similar plan with cHT."

Looking at all of this Geneseo noise, and reflecting on Intel's "innovation" in 2000 through 2009, from copper through AMD 64 to CSI, brings new meaning to their cherished term "copy exactly". But they can't even get that right.

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From: amie33311/16/2006 7:35:02 AM
of 273510
 
hexus.net.

"I know and trust AMD management will do whatever it takes to make the right moves, and we will continue to support them because we believe in offering our customers choices.

In the end I believe the integration with ATI will be very successful and AMD will come back with a vengeance. By then Intel will most likely be ready as Paul Otenelli is proving to be a very effective leader -- turning around a giant sinking ship and leaning out the fat organization in a matter of months.

I’ve said it before and I’ll say it again, Intel should thank AMD for forcing them to change for the better. Now AMD needs to light a fire under their engineers – they can’t live in the glory days of 2005, they have to move quickly!"

Lots more at the link.

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