Technology StocksWDC/Sandisk Corporation

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To: FUBHO who wrote (52320)2/22/2012 12:42:16 PM
From: Sam
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I am not as sure as you appear to be that Eli is actually saying anything different; maybe he is just saying the same thing in a different way? But, since I won't claim to actually have an especially deep understanding of these things, I also won't claim to be certain about that!

In any case, here is a post from Savo, from a couple of months ago, on this topic. Savo notes, among other things, that Sandisk was advertising for a manager of the "SanDisk 3D ReRAM team" last August ( ). It is not a new development.

3D NAND and 3D ReRAM

Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn’t get to in the first two posts, which I’ll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory technologies, specifically ReRAM.

Conceptually in many respects, 3D NAND is closer to a post-NAND technology than it is to NAND as we know it today. The slide below from a 2009 Toshiba presentation tells the tale.

From the left, floating gate NAND rolls along to where the path splits with ever smaller NAND geometries above and 3D NAND and other post-NAND technologies below. Other post-NAND include PCRAM, ReRAM, MRAM, etc.

What’s interesting is that 3D NAND is on the post-NAND branch and not on the NAND branch. Apparently this is because for 3D NAND the NAND string is perpendicular to the Silicon Substrate and other post-NAND technologies will depend on a similar three dimensionality.

Another slide from this same Toshiba presentation makes the point a different way.

In the center is the BiCS 3D Technology. Other technologies, including NAND and ReRam surround BiCS as potential extensions of BiCS 3D technology.

The point here is that BiCS technology can be applied to various memories to produce low cost data storage devices. When applied to NAND, the result is 3D BiCS-style NAND. When applied to ReRAM, the result will be 3D BiCS-style ReRAM and so forth.

BiCS is short for Bit-Cost Scalable technology. It is a 3D design strategy and as such allows greater capacity per footprint, which in turn results in lower bit cost. BiCS uses “a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layers to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material.”

Another Toshiba slide from this same presentation graphs the relation between capacity and bit cost. As one would expect, the more layers, the lower the cost. With BiCS, more layers and hence lower costs per bit can be achieved.

BiCS Flash appears to have the potential of a 10 Tbit/ chip.

At the bottom of the slide, Toshiba innocently wonders whether the market would be interested in such “huge” capacity?

Given cloud data center demands today, I doubt anyone is worrying about that one today- If the cost is right.

Toshiba has it right. Future trends will primarily be driven by cost per bit. The technology that will provide the most bits at the lowest cost will succeed.

Cost reduction is the most important issue.

For anyone interested in this Toshiba presentation, here is the link.

3D Resistive Random-Access Memory (RRAM)

RRAM and SanDisk/Toshiba’s 3D R/W technology deserves it’s own post, which hopefully I’ll get to in the not so distant future.

Suffice it to say, that it sure sounds like today SanDisk/Toshiba’s 3D R/W is RRAM.

Yoram apparently said as much at this year’s Flash Memory Summit:

“Further in the future, chip makers including SanDisk are developing 3-D structures that use changes in resistance to create denser chips. But the so-called resistive RAM will require EUV tools, he [Yoram Cedar] said.”

SanDisk has been looking for a new manager for its “3D ReRAM” team since August.

The interrelationship between BiCS 3D NAND and 3D RRAM bears watching.

Toshiba and SanDisk have licensed or otherwise invested in each other’s 3D technologies and today are co-developing both.

In 2008 SanDisk licensed it’s 3D R/W technology to Toshiba.

Then in Q1 2011, SanDisk “made an incremental strategic technology investment with Toshiba that covers a variety of technologies including a three-dimensional NAND architecture, known as Bit Cost Scalable or BiCS, which Toshiba had been developing independently.”


Many companies have been working on RRAM, for a long time. A very, very long time- which in some respects is a good thing.

Most importantly, the patents on the basic RRAM switching concepts apparently have expired.

The slide below is from a Deepak C. Sekar presentation. Deepak is Chief Scientist at MonolithIC 3D Inc. He also spent almost three years at SanDisk working on both NAND and 3D crosspoint memory.

Deepak makes three points about RRAM IP in the slide above:

Patents, if any, on the basic switching concepts have expired.

Good patents on more advanced concepts exist (eg) Pt-replacement approaches, array architectures, doping, etc.

IP scenario for RRAM a key advantage. Other resistive memories have gate-keepers (eg) Basic patents on PCM, CB-RAM, STT-MRAM fro Ovonyx, Axon Technologies, Grandis.

I suspect SanDisk and Toshiba have a particularly nice hand of good patents on the more advanced RRAM concepts, specifically array architectures.

The slide below is from SanDisk’s 2010 Investor Day.

Eli makes the point that SanDisk holds “Fundamental patents in 3D diode arrays (apply to most 3D approaches)”

I’m going to end with this slide from the IMEC consortium. Its a nice summary showing floating gate NAND, 3D Vertical NAND, and RRAM graphed against Cost/Bit and chip capacity.

Here is the article where the slide above was taken. Apparently Toshiba/SanDisk hasn’t signed up for the collaborative effort.

“IMEC is working collaboratively with major memory manufacturers including Elpida, Hynix, Micron and Samsung on both flash and follow-on memory roadmaps

Toshiba [Sandisk] is a notable absentee from the program.”

There could be many reasons why Toshiba/SanDisk wouldn’t be interested in working with IMEC.

One would be that Toshiba/SanDisk feel they have the inside track on the roadmap.

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To: Bruno Cipolla who wrote (52316)2/22/2012 2:20:23 PM
From: Charlie Smith
1 Recommendation   of 60323
As I've been saying, the Yen is cracking; could be a decent tailwind for SNDK. Lots of other headwinds, but this sure helps.

See my comments here, at approx the 4 minute mark:

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To: Charlie Smith who wrote (52329)2/23/2012 11:22:22 AM
From: Mbert
   of 60323
Looks like you have an audience Charlie. Well done.

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From: growthstocks2/23/2012 12:37:55 PM
   of 60323
Sold at $48.90, close enough to $49. It's been fun here, and thanks for the interesting dialogue. I wish you all luck, my closing comments are that this is not a growth stock and it's days are over for that. Hopefully they succeed with the new technology but until they do that, it will trade poorly and at low valuations in my opinion.

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To: growthstocks who wrote (52331)2/23/2012 1:31:35 PM
From: clean86
1 Recommendation   of 60323
Best of luck in your trading and may you find a stock to play that doesn't require dramamine!

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To: Sam who wrote (52328)2/23/2012 3:07:51 PM
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Apparently, it has always been SanShiba's plan to replace the diode array with resistive RAM, a point I previously missed.


What happened after the acquisition by SanDisk?
SanDisk and Toshiba announced a few years back that they are jointly working on the Matrix technology. The partners said they are trying to replace the antifuse with a rewritable memory element such as phase-change memory or resistive RAM. Please see a slide shown at SanDisk's 2010 analyst day (on the right). Yours truly worked on that project for almost 2 and a half years.What do I think of the technology? Well, that's a story for another day!!! And one that will require several security clearances...

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To: Sam who wrote (52328)2/23/2012 3:55:54 PM
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Understanding TLC NAND

by Kristian Vättö on 2/23/2012 1:14:00 PM
Posted in Storage , SSDs , TLC , OCZ , Indilinx Everest
A Brief Introduction to SSDs and Flash Memory

In almost every SSD review we have published, Anand has mentioned how an SSD is the biggest performance upgrade you can make today. Why would anyone use regular hard drives then? There is one big reason: price. SSD prices are still up in the clouds when compared to hard drive prices (especially before the Thailand floods) so for many, SSDs have not been a realistic option.

Forking over $700 for a 512GB SSD sounds crazy because a 500GB hard drive can be had for less than $50. Smaller capacities like 64GB and 128GB can already be bought for around $100 and $200 respectively, but unless you have the ability to have an SSD plus hard drive combo, such a small SSD doesn't usually cut it. If you have a desktop, the SSD + HDD combo should not be a problem but many laptops only have space for one 2.5" drive (unless you are willing to mod it afterwards by replacing the optical drive). SSD prices have been dropping for years now, but if the current rate continues it will take years before a $399 Walmart PC includes a reasonable size SSD. So what can be done?

Most of the time, SSD production costs are cut by shrinking the NAND die. Shrinking the die is the same as with CPUs: you move to a smaller manufacturing process, e.g. from 34nm to 25nm. In flash memory, this means you can increase the density per die and usually the physical die size is also smaller, meaning more dies from a single wafer. A die shrink is an effective way to lower costs but moving from one process to another takes time and the initial ramp of the new flash isn't necessarily cheaper. Once the new process has matured and supply has met demand, prices start to fall.

Since die shrinks are a relatively slow way to lower SSD prices and only contribute to steady reduction of prices, anyone looking to push higher capacity SSDs into the mainstream today will need something more. Right now, that "something more" is called Triple Level Cell flash, commonly abbreviated as TLC.

Rather than shrinking the die to improve density/capacity, TLC (like MLC) increases the number of bits per cell. In our SSD Anthology article, Anand described how SLC and MLC flash work, and TLC works the same way but takes things a step further. Normally, you apply a voltage to a cell and keep increasing it until you reach a point where the result is far enough from the "off" state that you now consider the cell as being "on". This is how SLC works, storing one bit per cell. For MLC, you store two bits per cell, which means instead of two voltage states (0 and 1) you have four states (00, 01, 10, 11). TLC takes that a step further and stores three bits per cell, or eight voltage states (000, 001, 010, 011, 100, 101, 110, and 111). We will take a deeper look into voltage states and how they work in the next page.

Even though SLC, MLC and TLC operate the same way, there is one crucial difference. Lets take a look at what happens to a NAND array depending on the amount of data per cell. The image above is a NAND array with ~16 billion transistors (one transistor is required per cell), i.e. 16 gigabits (Gb). This array can be turned into either SLC, MLC, or TLC. The actual array and transistors are equivalent in all three flash types; there is no physical difference. In the case of SLC flash, only one bit of data will be stored in one cell, hence your final product has a 16Gb capacity. When you up the bits per cell to two (MLC), you get 32Gb because now you have two bits per cell and there are still 16 billion cells. Likewise, three bits per cell (TLC) yields 48Gb.

However, TLC is a horse of slightly different color in this case. Capacities usually go in powers of two (2, 4, 8, 16 and so on) and 48 is not a power of two. To get a number that is a power of two, the original NAND array is chopped down. In our example, the array must be 10.67Gb in order to be 32Gb with three bits per cell, but since that is the same capacity as an MLC die, what is the benefit? You don't get more storage per die, but the actual die is smaller because the original 16Gb array has been reduced to a 10.7Gb array. That means more dies per wafer and hence lower cost.

Cell TypeSLCMLCTLCPrice per GB$3.00$0.90$0.60

Prices provided by OCZ

The theoretical price advantage of TLC isn't as great as SLC versus MLC, but it's still significant. In percentage, that is over a 30% reduction. The main reason is that MLC provides twice the capacity when compared to SLC (2bits per cell versus 1bit per cell), whereas TLC provides only 50% more than MLC (3bits per cell versus 2bits per cell). In fact, the price difference between MLC and TLC is directly proportional. TLC die is 33% smaller than a similar MLC die and in the prices provided by OCZ, TLC is also 33% cheaper than MLC. In theory, SLC should follow this equation as well and be priced at $1.80/GB, but there's limited 2Xnm SLC out in the wild, making SLC significantly more expensive than MLC and TLC at this point.

The reality of the matter is a little less clear. TLC NAND today isn't all that much cheaper than MLC NAND, which has contributed to its relative absence in the consumer SSD space. There's also a lack of controller support and market interest, which contribute to the higher prices of course.


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To: FUBHO who wrote (52334)2/23/2012 4:21:52 PM
From: Sam
   of 60323
interesting piece, thanks for posting it.

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To: FUBHO who wrote (52334)2/23/2012 4:51:36 PM
From: Mbert
   of 60323
This comment caught my eye:

There have been a few products already mixing an SSD with a HDD to allow oft-used data to be quickly read and written while rarely used bulk data that get's streamed (rather than random access) e.g. video is relegated to the HDD. Why not do the same with two grades of NAND? A few GB of SLC (or MLC) for OS files and frequently accessed and rewritten program files, and several hundred GB of TCL (or QLC, etc) for less frequently written data that it is still desirable to access quickly (e.g. game textures & FMVs). Faster than a HDD hybrid, cheaper than an all-SLC/MLC design, and just as fast in the vast majority of consumer use cases (exceptions including non-linear video editing, large-array data processing).

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To: FUBHO who wrote (52333)2/23/2012 5:56:24 PM
From: Bargain Hunter
   of 60323
Nice find. The author of that blog post seems to be Deepak Sekar.

I was aware that SanDisk's 3D R/W plans were to replace the Matrix diode array by cells with resistance changes. I think they must have recently chosen to use the term ReRAM to help distinguish what they used to call 3D from other 3D projects inside and outside SanDisk, including 3D NAND variants such as BiCS. Or perhaps they want to indicate that other companies working on ReRAM are not ahead of them.

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