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To: FUBHO who wrote (52320)2/22/2012 9:25:29 AM
From: Sam
   of 58035
 
ISSCC: SanDisk set to show highest density NAND flash
Peter Clarke 2/22/2012 7:13 AM EST
eetimes.com

LONDON – SanDisk Corp. is expected to report one of the highlights of the International Solid-State Circuits Conference, being held in San Francisco, when it provides details of a NAND flash memory implemented in 19-nm CMOS.

The chip, set to be discussed in paper 25.8 in the non-volatile memory session of ISSCC, is a 128-Gbit monolithic device that stores 3-bits per memory cell, is the highest density IC ever produced. The chip also has a 3-bit per cell write performance of 18-Mbyte per second and a read throughput of 400-Mbits per second.

The technology is described as proof that 3-bit per cell NAND has reached a level of maturity equivalent to 1- and 2-bit per cell NAND and will be welcomed for use as motherboard memory in applications such as tablet computers and smartphones and for solid-state drives (SSDs).

In the competitive world of NAND flash memory it will not be long before this memory is in commericial production. Other papers at ISSCC can discuss technologies and circuit ideas that are two, four or more years away from possible commercial implementation.

SanDisk has a roadmap that sees 19-nm NAND flash entering production in 2012, followed by a 1Y-nm process lowering the cost of 128-Gbit memory ICs in 2013 and a 1Z-nm process taking monolithic memory to 256-Gbits late in 2014. "We believe NAND technology will scale for a few more generations," Ritu Shrivastava, vice president of technology development at SanDisk told analysts recently.

Samsung Electronics Co. Ltd. is also set to present a sub-20nm NAND flash memory at ISSCC and with a higher read throughput of 533-Mbits per second. However the memory capacity is lower than SanDisk's at 64-Gbit.

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To: Sam who wrote (52323)2/22/2012 10:06:37 AM
From: Sam
   of 58035
 
The PR from Sandisk is much more informative than Peter Clarke reported. My bolding below.


SanDisk Develops World’s Smallest 128Gb NAND Flash Memory Chip
    Highest-capacity single die NAND flash memory chip extends leadership in three-bit per cell technology

    Paper outlining achievement to be delivered at technical conference
MILPITAS, Calif.--(BUSINESS WIRE)--Feb. 22, 2012-- SanDisk Corporation (NASDAQ: SNDK), a global leader in flash memory storage solutions, today announced it has developed the world’s smallest 128 gigabit (Gb)* NAND flash memory chip currently in production. The semiconductor device can store 128 billion individual bits of information on a single silicon die 170mm2 in size – a little more than a quarter of an inch squared, or smaller than the area covered by a U.S. penny.

The use of NAND flash memory in high tech equipment like smartphones, tablets and solid state drives (SSDs) allows advances in the full function, small form factor devices that are highly valued by consumers. Shrinking the size of NAND flash memory allows smaller, more powerful computing, communications and consumer electronics devices to be built while keeping costs low.

SanDisk built the 128Gb NAND flash memory chip on the company’s industry-leading 19 nanometer (nm) process technology. A nanometer measures one-billionth of a meter, meaning that 19nm circuit lines are so small that about 3,000 of them could fit across the width of a human hair. The chip also employs SanDisk’s three-bit per cell (X3) technology that allows the company to build NAND flash memory products with the ability to read and write three bits of information in each memory cell.

At 19nm, SanDisk is deploying its ninth generation of multi-level cell (MLC) NAND products and fifth generation of X3 technology. This combination of manufacturing and technical expertise helps SanDisk pack more information into each memory cell making it possible to create a smaller, denser NAND flash memory chip.

“Building a 128Gb NAND flash memory chip with this level of complexity is an incredible achievement,” said Mehrdad Mofidi, vice president, Memory Design. “This innovation allows SanDisk to continue to be a leader in helping our customers deliver smaller, more powerful products capable of doing more at lower cost.”

In addition to reduced size, the 128Gb semiconductor device has an industry-leading X3 write performance of 18 megabytes (MB)** per second. This level of performance is achieved using SanDisk’s patented advanced all bit line (ABL) architecture and means that X3 technology could be extended to certain product categories that use MLC NAND flash memory. A technical paper outlining the breakthrough will be presented at the International Solid-State Circuits Conference (ISSCC) in San Francisco today.

The 128Gb NAND flash memory chip was developed jointly by teams from SanDisk and Toshiba at SanDisk’s Milpitas campus. The effort was led by Yan Li, director of Memory Design at SanDisk. Products based on the 128Gb three-bit per cell technology began shipping late last year and have already started to ramp into high volume production. SanDisk has also developed a derivative product based on the success of the 128Gb chip – a 64Gb, X3 NAND flash memory chip that is compatible with the industry-standard microSD™ format. The company has also started to ramp production of this additional chip technology.

NAND flash memory is the technology behind the high reliability, small form factor storage solutions that SanDisk sells to OEM customers for use in a wide variety of products such as smartphones, tablets and Ultrabooks. It is also the technology used in products SanDisk sells through its retail channel in the form of imaging and mobile cards, USB drives and mp3 players.

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To: Sam who wrote (52323)2/22/2012 10:15:41 AM
From: Mbert
   of 58035
 
It looks like Peter read your post Sam. He updated his story to reflect the SNDK PR language. You are good!

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To: Mbert who wrote (52325)2/22/2012 10:18:50 AM
From: Sam
   of 58035
 
I saw that, and updated my post as well, deleting that part of it.

It has nothing to do with me being good, it has to do with Clarke reading the PR more carefully.

Here is Clarke's new piece. He should edit it again to spell "commericial" correctly.


ISSCC: SanDisk set to show highest density NAND flash
Peter Clarke 2/22/2012 7:13 AM EST

LONDON – SanDisk Corp. is expected to report one of the highlights of the International Solid-State Circuits Conference, being held in San Francisco, when it provides details of a NAND flash memory implemented in 19-nm CMOS.

The chip, set to be discussed in paper 25.8 in the non-volatile memory session of ISSCC, is a 128-Gbit monolithic device that stores 3-bits per memory cell, is the highest density IC ever produced. The chip also has a 3-bit per cell write performance of 18-Mbyte per second and a read throughput of 400-Mbits per second. The chip is a rectangle of silicon of 170 square millimeters area.

The technology is described as proof that 3-bit per cell NAND has reached a level of maturity equivalent to 1- and 2-bit per cell NAND and will be welcomed for use as motherboard memory in applications such as tablet computers and smartphones and for solid-state drives (SSDs).

In the competitive world of NAND flash memory this device is already in commericial production. Other papers at ISSCC can discuss technologies and circuit ideas that are two, four or more years away from possible commercial implementation.

SanDisk has a roadmap that sees 19-nm NAND flash ramping production in 2012, followed by a 1Y-nm process lowering the cost of 128-Gbit memory ICs in 2013 and a 1Z-nm process taking monolithic memory to 256-Gbits late in 2014. "We believe NAND technology will scale for a few more generations," Ritu Shrivastava, vice president of technology development at SanDisk told analysts recently.

The 128-Gbit NAND flash memory chip was developed jointly by teams from SanDisk and Toshiba at SanDisk's Milpitas campus. The effort was led by Yan Li, director of Memory Design at SanDisk. Products based on the 128-Gbit three-bit per cell technology began shipping late last year and have already started to ramp into high volume production. SanDisk has also developed a derivative product, a 64-Gbit NAND flash memory chip that is compatible with the industry-standard microSD format. The company has also started to ramp production of this additional chip technology.

Samsung Electronics Co. Ltd. is also set to present a sub-20nm NAND flash memory at ISSCC and with a higher read throughput of 533-Mbits per second. However the memory capacity is lower than SanDisk's at 64-Gbit.

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To: Sam who wrote (52326)2/22/2012 10:24:57 AM
From: Mbert
   of 58035
 
You know you can comment directly on the EETimes story don't you? The authors are pretty good about reading and responding to comments. You could also ask him about his MU bias while you're at it.

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To: FUBHO who wrote (52320)2/22/2012 12:42:16 PM
From: Sam
1 Recommendation   of 58035
 
I am not as sure as you appear to be that Eli is actually saying anything different; maybe he is just saying the same thing in a different way? But, since I won't claim to actually have an especially deep understanding of these things, I also won't claim to be certain about that!

In any case, here is a post from Savo, from a couple of months ago, on this topic. Savo notes, among other things, that Sandisk was advertising for a manager of the "SanDisk 3D ReRAM team" last August ( simplyhired.com ). It is not a new development.


3D NAND and 3D ReRAM
savolainen.wordpress.com


Time to wrap up this first pass at 3D NAND. There are a couple of points which I didn’t get to in the first two posts, which I’ll touch on here. Of particular interest is the relationship of 3D NAND to future post-NAND memory technologies, specifically ReRAM.

Conceptually in many respects, 3D NAND is closer to a post-NAND technology than it is to NAND as we know it today. The slide below from a 2009 Toshiba presentation tells the tale.



From the left, floating gate NAND rolls along to where the path splits with ever smaller NAND geometries above and 3D NAND and other post-NAND technologies below. Other post-NAND include PCRAM, ReRAM, MRAM, etc.

What’s interesting is that 3D NAND is on the post-NAND branch and not on the NAND branch. Apparently this is because for 3D NAND the NAND string is perpendicular to the Silicon Substrate and other post-NAND technologies will depend on a similar three dimensionality.

Another slide from this same Toshiba presentation makes the point a different way.



In the center is the BiCS 3D Technology. Other technologies, including NAND and ReRam surround BiCS as potential extensions of BiCS 3D technology.

The point here is that BiCS technology can be applied to various memories to produce low cost data storage devices. When applied to NAND, the result is 3D BiCS-style NAND. When applied to ReRAM, the result will be 3D BiCS-style ReRAM and so forth.

BiCS is short for Bit-Cost Scalable technology. It is a 3D design strategy and as such allows greater capacity per footprint, which in turn results in lower bit cost. BiCS uses “a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layers to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material.”

Another Toshiba slide from this same presentation graphs the relation between capacity and bit cost. As one would expect, the more layers, the lower the cost. With BiCS, more layers and hence lower costs per bit can be achieved.



BiCS Flash appears to have the potential of a 10 Tbit/ chip.

At the bottom of the slide, Toshiba innocently wonders whether the market would be interested in such “huge” capacity?

Given cloud data center demands today, I doubt anyone is worrying about that one today- If the cost is right.



Toshiba has it right. Future trends will primarily be driven by cost per bit. The technology that will provide the most bits at the lowest cost will succeed.

Cost reduction is the most important issue.

For anyone interested in this Toshiba presentation, here is the link.

3D Resistive Random-Access Memory (RRAM)

RRAM and SanDisk/Toshiba’s 3D R/W technology deserves it’s own post, which hopefully I’ll get to in the not so distant future.

Suffice it to say, that it sure sounds like today SanDisk/Toshiba’s 3D R/W is RRAM.

Yoram apparently said as much at this year’s Flash Memory Summit:

“Further in the future, chip makers including SanDisk are developing 3-D structures that use changes in resistance to create denser chips. But the so-called resistive RAM will require EUV tools, he [Yoram Cedar] said.”

SanDisk has been looking for a new manager for its “3D ReRAM” team since August.

The interrelationship between BiCS 3D NAND and 3D RRAM bears watching.

Toshiba and SanDisk have licensed or otherwise invested in each other’s 3D technologies and today are co-developing both.

In 2008 SanDisk licensed it’s 3D R/W technology to Toshiba.

Then in Q1 2011, SanDisk “made an incremental strategic technology investment with Toshiba that covers a variety of technologies including a three-dimensional NAND architecture, known as Bit Cost Scalable or BiCS, which Toshiba had been developing independently.”

RRAM IP

Many companies have been working on RRAM, for a long time. A very, very long time- which in some respects is a good thing.

Most importantly, the patents on the basic RRAM switching concepts apparently have expired.

The slide below is from a Deepak C. Sekar presentation. Deepak is Chief Scientist at MonolithIC 3D Inc. He also spent almost three years at SanDisk working on both NAND and 3D crosspoint memory.



Deepak makes three points about RRAM IP in the slide above:

Patents, if any, on the basic switching concepts have expired.

Good patents on more advanced concepts exist (eg) Pt-replacement approaches, array architectures, doping, etc.

IP scenario for RRAM a key advantage. Other resistive memories have gate-keepers (eg) Basic patents on PCM, CB-RAM, STT-MRAM fro Ovonyx, Axon Technologies, Grandis.

I suspect SanDisk and Toshiba have a particularly nice hand of good patents on the more advanced RRAM concepts, specifically array architectures.

The slide below is from SanDisk’s 2010 Investor Day.



Eli makes the point that SanDisk holds “Fundamental patents in 3D diode arrays (apply to most 3D approaches)”

I’m going to end with this slide from the IMEC consortium. Its a nice summary showing floating gate NAND, 3D Vertical NAND, and RRAM graphed against Cost/Bit and chip capacity.





Here is the article where the slide above was taken. Apparently Toshiba/SanDisk hasn’t signed up for the collaborative effort.

“IMEC is working collaboratively with major memory manufacturers including Elpida, Hynix, Micron and Samsung on both flash and follow-on memory roadmaps

Toshiba [Sandisk] is a notable absentee from the program.”

There could be many reasons why Toshiba/SanDisk wouldn’t be interested in working with IMEC.

One would be that Toshiba/SanDisk feel they have the inside track on the roadmap.

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To: Bruno Cipolla who wrote (52316)2/22/2012 2:20:23 PM
From: Charlie Smith
1 Recommendation   of 58035
 
As I've been saying, the Yen is cracking; could be a decent tailwind for SNDK. Lots of other headwinds, but this sure helps.

See my comments here, at approx the 4 minute mark:

video.cnbc.com

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To: Charlie Smith who wrote (52329)2/23/2012 11:22:22 AM
From: Mbert
   of 58035
 
Looks like you have an audience Charlie. Well done.

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From: growthstocks2/23/2012 12:37:55 PM
   of 58035
 
Sold at $48.90, close enough to $49. It's been fun here, and thanks for the interesting dialogue. I wish you all luck, my closing comments are that this is not a growth stock and it's days are over for that. Hopefully they succeed with the new technology but until they do that, it will trade poorly and at low valuations in my opinion.

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To: growthstocks who wrote (52331)2/23/2012 1:31:35 PM
From: clean86
1 Recommendation   of 58035
 
Best of luck in your trading and may you find a stock to play that doesn't require dramamine!

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