NEC explores multi-level cells
for future high-density DRAMs
By Will Wade
PORTLAND, Ore.--Facing a double-edged sword of continuing demand for higher density memories and ever-increasing price pressures, NEC Corp. is experimenting with multi-level cell (MLC) technology for DRAMs, said a company manager here during a technical conference on advanced wafer processing.
The move to multi-level cell technology will require a drastic redesign of current DRAM architecture, but it also promises to significantly boost storage, said Takashi Okuda, senior manager of memory design and development at NEC Corp.'s ULSI device development labs in Kanagawa, Japan.
During the Silicon Wafer Symposium hosted by Semiconductor Equipment and Materials International (SEMI) this week, Okuda said NEC's MLC DRAMs were very much in the development stages, but could eventually be manufactured in multi-gigabit densities.
NEC's current DRAM roadmap through the year 2000 is dominated by standard SDRAM and Rambus memory, and Okuda said any possible deployment of MLC DRAM was not expected for at least several years beyond that. A key element of the design is using a high-dielectric material, which can increase the capacity of the chip's capacitors.
Multi-level cell technology is already used for flash memory chips, allowing a memory cell to store two or more bits of data, as compared to the traditional single-bit cells. However, the technique requires much more precision in order to create cells with four or more energy states instead of the simples cells that are either "on" or "off."
News of NEC trying to apply multi-level cell technology to DRAMs drew a skeptical response from memory analyst Bruce Bonner at Dataquest in San Jose. "Using MLC is a total departure from standard DRAMs, and there are a lot of negatives," Bonner said. He noted that flash memory is better suited for the architecture because it is based on analog technology, while engineers will face numerous hurdles in creating the more complex cells for digital DRAM chips.
"It's a really big deal to go to cell designs with more than two levels," he said. Bonner also noted that MLC technology is likely to be slower than existing DRAMs, which bucks the current trend of faster memory chips seen in double data rate DRAM and Rambus DRAM.
But, Bonner did not completely discount NEC's efforts, pointing out the Samsung Electronics Co. Ltd. has recently sampled a 1-gigabit DRAM chip that also used high dielectric material to increase its storage capabilities (see Sept.24 story).
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