Micron / Samsung TSV stacked memory collaboration: a closer look
Samsung Electronics and Micron Technology have created an industry group to collaborate on the implementation of an open interface specification for a new memory technology called the Hybrid Memory Cube (HMC).
More infomation on the Hybrid Memory Cube (HMC) here.
The stated goal of the Consortium is to “…facilitate HMC Integration into a wide variety of systems, platforms and applications by defining an adoptable industry-wide interface that enables developers, manufacturers and enablers to leverage this revolutionary technology”.
Samsung has had a long list of research and commercial announcements since their initial indications that stacking DRAM was on their roadmap in 2006 [ see for example : “ Samsung presents new 3D TSV Packaging Roadmap”; “ New Samsung 8GB DDR3 module utilizes 3D TSV technology”; “ 3D Integration entering 2011”; “ Samsung Wide-IO Memory for Mobile Products: A Closer Look”; “ Samsung develops 32GB RDIMM using 3D TSV technology”.
Micron has been working for many years on TSV stacking technology and earlier this yearrevealed their intent to enter the stacked DRAM arena with what they called a hyper memory cube [see “ Hyper Memory Cube” 3DIC Technology].
It is thus of interest to understand how/why Samsung and Micron have joined forces in this new consortium.
TSV stacked memory with a controller layer addresses the so called "memory wall" problem. Essentially, DRAM performance today is constrained by the capacity of the data channel that sits between the memory and the processor. No matter how much faster the DRAM chip itself gets, the channel typically chokes on the capacity. Systems are not able to take advantage of new memory technologies because of this latency issue – they need more bandwidth.
The HMC which is now being called a “hybrid memory cube” is a stack of multiple thinned memory die sitting atop a logic chip bonded together using TSV. This greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs.
The controller layer in the HMC is the key to delivering the performance boost, allowing a higher speed bus from the controller chip to the CPU and the thinned and TSV connected memory layers mean memory can be packed more densely in a given volume. The HMC requires about 10% of the volume of a DDR3 memory module.
The interface in the control layer is totally different from current DDR implementations and thus the need for a consortium of the major players to standardize this interface.
Micron HMC : (A) schematic representation; (B) showing TSV; (C) the real module
It is claimed that the technology provides 15X the performance of a DDR3 module, uses 70% less energy per bit than DDR3 and uses 90% less space than todays RDIMMs. Current DRAM burns a huge amount of the power in laptops and phones. HMC draws less power because of the wider I/O capabilities and greater I/O bandwidth significantly cut the amount of energy needed per bit - ~ 10% of the energy per bit of a DDR3 memory module.
DIMM vs HMC: 160 Gb/sec Equivalence (Courtesy of Micron Technology)
The prototype shown by Micron and Intel is reportedly rated at 128 Gbps. In comparison, DDR3-1333 modules offer a bandwidth of 10.66 Gbps, current DDR3-1600 devices deliver 12.8 Gbps and DDR4-when commercialized reportedly will achieve 21.34 Gbps.
HMC performance vs todays memory (Courtesy of Intel developer forum 2011)
Micron and Samsung will work with fellow founding members Altera, Open Silicon and Xilinx and hopefully others, to bring the technology to market. Specification for the HMC will be finalized next year. Still to be worked out is who manufactures the HMC.
Looking a little closer we find that Intel has been working closely with Micron on this development. At the recent Intel designer forum (IDF 2011) Intel CTO Justin Rattner demonstrated the Hybrid Memory Cube towards the end of his keynote lecture which can be seen here.
It is not clear at this point whether Intel owns part of the IP or not and it is not clear why Intel is not a member of the Micron / Samsung HMC consortium, but Intel certainly had high praise for the technology which they claim will allow them to continue to “improve the interconnect within computer systems so that communication between the microprocessor, DRAM, storage and peripherals is faster and lower power with each successive generation”Rattenr also stated that “This hybrid-stacked DRAM, known as the Hybrid Memory Cube (HMC), is the world’s highest bandwidth DRAM device with sustained transfer rates of 1 terabit per second. It is also the most energy efficient DRAM ever built. “
The industry always needs multiple sources for a broad adoption. The cross license agreements that exist between Samsung and Micron [ here] and Samsung and Intel [ here] probably made the formation of this consortium easier to happen.