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To: neolib who wrote (368)	1/28/2011 7:01:58 PM
From: pgerassi	of 9756

DDR3 controller in the layout includes the interface transistors which are large to drive the signals hard enough to handle 2 DIMMs. That is over 100 pins and those don't shrink with the rest as the process goes smaller. Remember this is a 74mm2 die. They are about half the size of those in the AthlonII and PhenomII dies because those have 2 channels of it, but since those dies are over twice as big, they don't seem to be as big relatively speaking. The PCIe and HT interfaces are much smaller than the DDR3 interface because they drive one load each instead of multiple loads (the clock pins drive every DRAM die on both DIMMs for example). You can buffer them on the DIMMs, but it costs 4 cycles of latency for DDR3, so you turn 9-9-9-27 into 13-13-13-39, which is quite expensive on many PC applications. Servers can handle it, because of many pending requests are in the queue. Throughput there is a bigger factor. The same is true for GPUs. So buffering is possible, but quite expensive on DIMMs, its simply cheaper and easier for the on die interface transistors to be able to handle the unbuffered load. $1 on the die is far cheaper than $5-20 on the DIMMs and the slowdown in applications at the same clock.