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To: Art Bechhoefer who wrote (92713)	6/23/2010 4:42:06 PM
From: FUBHO	Read Replies (1) of 117513

Apple's A4 is 7.3mm^2 in size. That would yield just about 1230 die candidates per wafer for a 300mm wafer. If we assume TSMC charges $4500 for a fully processed 45nm wafer at 65% yield, that would be a die cost of $6 per die. Then you have to package at say $1-2/die. The cost per chip would be around $7-8 per chip and they are currently charging about $25. I am going to add more cost for the extra core on the latest chip, but that is minimal. The current process is 65nm for Snapdragon, so the die of the chip would be larger, but the processed wafer cost would be cheaper. Lots of variables, but it definitely costs less than $10 a chip to make. There was a tremendous amount of rounding and assuming Please do your own math and see what you get. ================================================== Analytical die count estimation For any given wafer diameter [d, mm] and target IC size [S, mm2], there is an exact number of integral die pieces that can be sliced out of the wafer. The gross Die Per Wafer [DPW] can be estimated by the following expression: Note, that the gross die count does not take into account the die defect loss, various alignment markings and test sites on the wafer. en.wikipedia.org ifixit.com eetimes.com tsmc.com