Where did AM2 support two or more 16/16 HT links?
I never sait it did. But the core has them. 3 of them in Rev F and G cores, and 4 in Rev H. AMD just chose not to route them to pins (apparently).
We hoped that AMD would find a way, but they thought that the pins were needed more to allow split power to cores, XBAR and MCT.
True, but the number of pins in the socket was not dictated to AMD by anyone. Socket AM2 is not compatible with older sockets, so AMD could have chosen any number of pins they wanted. It is a tradeoff, I understand, and there may not have been enough left in the 939 pin budget to connect HT to pins (they could have increased it, but there certainly were enough pins in Socket 939, which AMD just didn't connect.
Disabling functionality has been Intel approach. AMD does not have to copy everything Intel does.
Imagine AMD left those HT ports there, making all 15M+ processors AMD will sell this quarter Torrenza compatible. And imagine someone, some third party, that believed in Torrenza more than AMD does, suppose this third party came up with some unique co-processor apealing to wide audience. AMD could walk away with this market, with intel unable to compete. Unfortunately, the Torrenza thing is available only on a very small number of high priced parts, severely limiting attractiveness of Third parties to come up with anything beyond small niche products. AMD closed the possibility of using it in wider range of products.
If you wanted to wait for HT3.0 on AM3, you would have two 8/8 cHT3.0 links using that one 16/16 port. If Intel would have gone to native quad core in Q3/07 instead of going again to the dual chip route, AMD could make AM3 based 4x4s MBs available. But, it is better this way with the socket F CPU determining what kind of memory is supported. And it was available faster.
I am hoping that that AMD has learned from the Socket AM2 f-up (that it had to go to Opteron socket for 4x4) and will not repeat the same mistake with AM3. But my money is on AMD making the same mistake again. Something like 4x4, or Torrenza capability should be available to all AM3 processors.
One mitigating factor would be higher capacity DRAM dies. One wonders why we are not seeing 1, 2 and 4Gb DRAM dies as Moore's law states we should? Most unbuffered DIMMs still use 512Mb DRAM dies. By using 4Gb dies, instead of the typical 512Mb, we would have 4 and 8GB unbuffered DDR2 DIMMs and 16GB buffered DDR2 DIMMs. That would allow AM2 CPUs to have 32GB of memory (128GB, if they could use buffered DDR2).
According to Samsung, 1 Gbit should be mainstream this year. I didn't check on the recent modules I got (since they have a heat spreaders over chips, so I don't know if they use 512 or 1 Gbit. Samsung is apparently going to switch to 2 Gbit in 2007:
They seem to be foreseeing DDR3 in 2007 as well. We will see how that turns out...
BTW, Samsung forecasts over 5 GB of memory per PC system in 2009. (Page 8)