|3-D requires system rethink|
(08/21/2006 9:00 AM EDT)
The rising interest in system-in-package combina- tions of memory and logic ICs is paving the way for a more complex form of 3-D integration: through-via interconnects. Although skeptics argue that problems related to cost, thermal load, electromigration and design complexity could keep such 3-D solutions on the back burner indefinitely, optimists are confident that breakthrough chips with through-via interconnects will arrive over the next few years.
Through-via interconnections are formed by etching or laser-drilling holes directly through chips and then filling the via holes with metal to connect the top chip to the lower one. The use of such connections can reduce the physical area of the chip stack and shorten the interconnect distance between the logic function on one chip and the logic block on a second chip. The shorter distances, in turn, shorten signal delays and thereby speed overall operation.
Vertical chip-stacking solutions should be thought of as a continuum, counsels Bob Jones, manager of system interconnect solutions at Freescale Semiconductor Inc. Some applications might call for existing designs connected through perimeter bond pads, creating a space-saving, "minimal footprint" vertical stack. Other applications call for "a rethink of the architectures" of the conjoined devices, using dense through-via interconnects, Jones said.
"For some applications, we can still go quite a way forward by using bond pad connections and remapping into a 3-D solution," he said. "The next level is to use global interconnects without redefining the chips. As we move forward with 3-D, we get into a redefinition of the architectures."
Indeed, several companies have implemented 3-D technologies at various levels of complexity. MtekVision Co. Ltd. (Seoul, South Korea) has used vertical connections and wafer-level processing techniques to create what it claims is the smallest camera control processor around, reducing the footprint by about 40 percent. Luxtera Inc. (Carlsbad, Calif.) has used vertical interconnects to create an all-silicon optical modulator solution for 10-Gbit/second transport. And Samsung Electronics, in a technology demonstration, has used laser drilling to create fairly large vias to connect no fewer than eight NAND flash memory chips.
Interest is brewing worldwide. At the Symposium on VLSI Circuits in Honolulu in June, Kenji Takahashi, a manager at Toshiba Corp.'s advanced packaging engineering group, described a low-cost Toshiba 3-D process that uses laser ablation to burn vertical holes for copper-plated, 10-micron vertical interconnects. The technology demonstration centered on an image sensor used in space-restricted mobile systems. The company has figured out how to use laser drilling without damaging the silicon, Takahashi said, although the active elements must be kept 10 microns or more from the surface of the vias.
In a plenary speech at the symposium, Takahashi outlined about a dozen 3-D packaging R&D efforts in Japan, Singapore and other Asian nations. A Japanese-government sponsored effort with NEC Electronics, Oki Electric and other partners is putting together a DRAM using 3-D connections. The approach divides the memory array and supports error-correction code (ECC) and address circuitry on different dice.
At International Sematech (Austin, Texas), a small program to study the infrastructure needs of 3-D chips is being headed by Sematech's Susan Vitkavage under the direction of Sitaram Arkalgud, a Freescale assignee who manages Sematech's interconnect program.
"The No. 1 business issue concerning 3-D is the unclear cost/benefit situation," Vitkavage said. To that end, Sematech is developing a method to study the trade-offs of taking a 2-D chip into the third dimension, including wafer-on-wafer and die-on-wafer approaches.
"There are two main camps: the form factor group, which wants more density in a smaller form factor, and the high-performance group, which sees 3-D as a means of getting past the memory bandwidth and signal-routing problems in 2-D," Vitkavage said. One benefit to 3-D chips is that two fairly small dice can be connected, replacing a much larger die that might pose yield problems.
"Several of the Sematech members are actively pursuing 3-D solutions," Arkalgud said, declining to be more specific.
The military sector is also active, with programs aimed at streaming image data into a 3-D memory-and-processor stack with dozens of interconnected dice. The Defense Advanced Research Projects Agency has funded several 3-D programs, studying, for example, the tight coupling of parallel-processing compute engines to memory and examining image processors for smart weapons.
Design tools remain a weak link in the 3-D infrastructure, with thermal modeling, finite-element analysis, multichip databases, floor-planning and layout tools all required for a smooth 3-D design flows. Lisa McIlrath, CEO of R3Logic Inc. (Cambridge, Mass.), a privately held company specializing in design services and 3-D EDA tools, said the company was founded in 2000 at the end of a five-year joint R&D program between Northeastern University and the Massachusetts Institute of Technology. McIlrath said R3Logic will intro- duce commercial EDA tools later this year.
Keith Felton, a product-marketing manager at Cadence Design Systems Inc.'s IC packaging tools division in Chelmsford, Mass., said system-in-package solutions are helping engineers understand the technical challenges standing in the way of through-via implementations. "SiPs are teaching us about co-design methodologies," in which the dice and the package are considered together early in the design process, Felton said.
As engineers create vertical stacks of logic and memory dice for use in pacemakers, hearing aids, PDAs, wireless handsets and other consumer products, "we are learning a lot," Felton said. The iPod Nano, for example, included a vertically connected stack of a PortalPlayer controller, a Samsung memory chip and a memory controller IC, he said. "Three years ago, SiPs were largely experimental. By 2008, they will be a huge part of the semiconductor market," Felton predicted.
Chicken and egg
The EDA tools needed for more-aggressive 3-D chips, with perhaps thousands of through-via interconnects, are stuck in a chicken-and-egg situation, he said. "EDA companies like Cadence are very good at writing applications software. But we need customers to come to us and say that they need a certain set of tools and that they plan to buy and use them," said Felton. "Until that happens, we will continue to sit and watch the market to see how the opportunity develops. We have not had anybody approach us with a solid business proposition yet."
Ted Vucurevich, chief technology officer at Cadence, said the EDA giant has been in regular discussions about design tool needs with Ziptronix Inc. (Morrisville, N.C.) and Tezzaron Semiconductor (formerly Tachyon Semiconductor; Naperville, Ill.), two pioneering companies in the 3-D field. Today's customers can use an existing Cadence flow and modify it with scripting routines, he said, adding that "there are only a couple of areas where there are real weaknesses." Vucurevich said that Cadence has been "tracking this technology since 2000, and we are really, really close. In the next few years, we are going to see a couple of high-volume examples of 3-D solutions that will drive the price down."
A company using a design with a big die size, in the 15 x 15-mm range, can sharply improve its yields by moving to a vertically connected stack of two much-smaller chips, in the 5 x 5-mm or 7 x 7-mm range. Gains also come because vertical interconnects are much shorter than wires stretching across a large die, with smaller capacitive and inductive loads, Vucurevich said.
But major performance improvements "don't come unless you design for it," he said. Today, the mechanical and electrical verification steps can be handled fairly readily. But if a design team seeks to take full advantage of 3-D technology, the processor and memory architectures need to be rethought. There are no tools today to do a true architectural exploration, taking advantage of the full 3-D context," Vucurevich said. In particular, such multichip designs require database technology that can adapt to multiple chips.
Nevertheless, Vucurevich said he is certain that two "significant, serious" companies, which he declined to identify, are readying commercial 3-D chips. "These are significant efforts, though they may not take advantage of all that 3-D has to offer," he said.
While processor-to-memory combinations may be the largest opportunity, Vucurevich said, "we should not become myopic" and ignore opportunities in "lab-on-a-chip" solutions, or combining heterogenous technologies for optoelectronic applications. Microelectromechanical systems are a nascent opportunity, again bringing components made from different materials into proximity.
"Three-D gives architects an amazing extra dimension," Vucurevich said.
But taking full advantage of 3-D requires a head-to-toe rethink of how computers are built, said Wilfried Haensch, manager of device and integration technology at IBM Corp.'s Thomas J. Watson Research Center (Yorktown Heights, N.Y.). "Today's system architecture can be accommodated with 2-D designs, even though they may suffer from limited bandwidth. The real attraction of 3-D comes when we get to 16 or 32 cores, where the architecture includes sharing a large L2 cache," he said.
Achieving the needed EDA tools and refining the manufacturing process are straightforward engineering problems that can be dealt with, Haensch said. The more difficult challenge is creating an architecture that might include an L2 die on the bottom and L3 on the top, serving a processor die in a vertical stack.
"Timewise, it will not be a short-term project. It might take five to 10 years to take full advantage. We will only do 3-D if we get a performance advantage--huge bandwidth between the processor and a memory stack--at reasonable cost," he said. And with any bare-die implementation, "test is a big issue," Haensch added.
Eric Beyne, a manager at the Interuniversity Microelectronics Center (Leuven, Belgium), said any 3-D process should start with a die-screening process to obtain "good enough dice" using self-test and Iddq test methods.
IMEC has developed a 3-D flow that introduces the vertical interconnects, which IMEC calls copper nails, after the transistor formation but prior to the back-end interconnect formation. The copper nails are created by plasma-etching a silicon hole, which is filled with copper and covered by an insulation layer and a chemical-mechanical-polishing stop layer.
The approach can be repeated for multidice stacks, but Beyne warns that connecting five dice, for example, requires that the starting yield for each wafer must be at 97 percent or better in order for the final module to exceed 80 percent yields, thereby meeting cost goals.
Bob Patti, chief technology officer at Tezzaron Semiconductor, has worked on 3-D technology for a decade. Later this year, Tezzaron will begin selling a high-performance 3-D "SRAM replacement" that Patti said will be less expensive to produce than existing high-end SRAMs. By putting the memory array on one level and ECC and redundancy on another, any defective bits can more easily be inspected and repaired, avoiding "the confluence of wires" seen on 2-D chips, Patti said. Also, the rows and columns are shorter, an important attribute for access times of 3 nanoseconds or less.
The company's first product, a 72-Mbit SRAM replacement, will benefit from better yields than seen for larger, 2-D SRAM dice, he said. "Our 3-D solution is more repairable, with smaller capacitances, and with manufacturing costs that are about one-half the cost per bit of making a conventional memory."
If Patti, who has been battling in the Z dimension for a decade, is the leading optimist, perhaps David Tuckerman, CTO of Tessera Inc. (San Jose, Calif.), is the leading critic. Tuckerman takes a conservative stance toward chips with through-via interconnects, which he called "a nichey, high-performance" technology.
"Through-via connections are a ways away from commercial reality," Tuckerman said, arguing that cell phones, for one, are better served by chip-scale packaging, including face-to-face, flip-chip combinations.
"Advanced packages are becoming more 3-D-like. Already, we can stack 64 memory chips in a space the size of a sugar cube," Tuckerman said. Many companies, such as Infineon Technologies, have studied through-via 3-D connections and backed away from the approach, partly because the known-good-dice problem makes it too costly, he said.
Even for very high-performance computing, Tuckerman said, taking advantage of 3-D, with tens of thousands of connections between the dice, will provide advantages "only if those companies come up with entirely new architectures." High-performance computing is limited not by interconnects, but by power consumption and thermal issues, he said. "And nobody is going to do something that is likely to add to costs."