TO you and Dale, Many items of the packet processor are a part of the C programming world and have been done at that level in slow speed environment. Now with that calliber of programming in a generic environment , what is necessary to achieve our goal is translate it into C++ (that which is necessary) and then combine the VHDL design files for the FPGA proto, integrate it on a core processor with some 200 to 300 mhz capability and 64 bit bus width, maybe some concatenating of data descriptors to further increase throughput working on 256 bit sub groups in a clock cycle in a pipeline.|
Sounds tricky it is. But add the tool set to manage this design environment, simulate it and create specialized instructions and debugger capability all within a typical design cycle of 6 mos.
And you got something.
The company is Tensilica, check it out. Intel uses them , Nortel uses them, I don't know about CSCO, they seem to buy everything.
We will use them as well.
But the concept is a replacement ASIC at 10 bucks, 10 times as powerful as the best DSP solution today. And custom fit to the application, be it gigabit routing, or gigabit ATM cell management
or multilink reprogrammable network interfaces.
It is THE direction of the next gen Networking solution. Either have it or find a new job. Here is where I said to myself to find another semi. Tensilica is at least 12 to18 mos from being public.